Revision History
Revision No.
0.01
0.02
0.03
0.04
0.05
0.06
0.07
History
Preliminary version release
Add temperature information in feature
update operation frequency
update IDD 1600,1866,2133
update IDD data
update IDD data (x8)
update Pakage Dimension (x16)
- Corrected Pakage Dimension
(Page 34 , 78 Balls to 96Balls)
update IDD data
Official Version Release
Official Version Release & Add L/J Part
Delete Comments regarding IDD6TC
& New revised logo (Hynix to SK hynix)
Draft Date
July. 2011
Aug. 2011
Oct. 2011
Nov. 2011
Nov. 2011
Dec. 2011
Dec. 2011
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
0.08
0.09
1.0
1.1
Feb.2012
Mar.2012
Apr.2012
May.2012
Page 24, all IDD specs are completed
Deleted “Preliminary”
Add L/J Part support
Page 12/17/24
Rev. 1.1 / May. 2012
2
Description
The H5TQ2G83DFR-xxC, H5TQ2G63DFR-xxC,H5TQ2G83DFR-xxI, H5TQ2G63DFR-xxI, H5TQ2G83DFR-
xxL,H5TQ2G63DFR-xxL,H5TQ2G83DFR-xxJ,H5TQ2G63DFR-xxJ are a
2,147,483,648-bit
CMOS Double Data
Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large
memory density and high bandwidth. SK Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations ref-
erenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on
the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are
sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched
to achieve very high bandwidth.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13
and 14 supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 8banks
• Average Refresh Cycle (Tcase
0
o
C~ 95
o
C)
- 7.8 µs at
0
o
C ~ 85
o
C
- 3.9
µs at 85
o
C ~ 95
o
C
Commercial Temperature(
0
o
C ~ 85
o
C)
Industrial Temperature(
-40
o
C ~ 95
o
C)
• JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch
* This product in compliance with the RoHS directive.
Rev. 1.1 / May. 2012
3
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