Description
SK hynix Unbuffered Small Outline DDR3 SDRAM DIMMs (Unbuffered Small Outline Double Data Rate Syn-
chronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules
that use DDR3 SDRAM devices. These Unbuffered DDR3 SDRAM SODIMMs are intended for use as main
memory when installed in systems such as mobile personal computers.
Fetures
•
•
•
•
•
•
•
•
•
•
VDD=1.5V +/- 0.075V
VDDQ=1.5V +/- 0.075V
VDDSPD=3.0V to 3.6V
8 internal banks
Data transfer rates: PC3-14900, PC 3-12800, PC3-10600,PC3-8500
Bi-directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly: BL 8 or BC (Burst Chop) 4
On Die Termination (ODT) supported
This product is in Compliance with the RoHS directive
Ordering Information
Part Number
HMT325S6EFR8C-G7/H9/PB/RD
HMT351S6EFR8C-G7/H9/PB/RD
Density
2GB
4GB
Organization
256Mx64
512Mx64
Component Composition
256Mx8(H5TQ2G83EFR)*8
256Mx8(H5TQ2G83EFR)*16
# of
ranks
1
2
Rev.1.3 /Sep. 2013
3
Pin Descriptions
Pin Name
CK[1:0]
CK[1:0]
CKE[1:0]
RAS
CAS
WE
S[1:0]
A[9:0],A11,
A[15:13]
A10/AP
A12/BC
BA[2:0]
ODT[1:0]
SCL
SDA
SA[1:0]
Description
Clock Input, positive line
Clock Input, negative line
Clock Enables
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Autoprecharge
Address Input/Burst chop
SDRAM Bank Addresses
On Die Termination Inputs
Serial Presence Detect (SPD)
Clock Input
SPD Data Input/Output
SPD Address Inputs
Num
ber
2
2
2
1
1
1
2
14
1
1
3
2
1
1
2
V
REFDQ
V
REFCA
V
TT
V
DDSPD
NC
Input/Output Reference
Termination Voltage
SPD Power
Reserved for future use
1
1
2
1
2
Total: 204
Pin Name
DQ[63:0]
DM[7:0]
DQS[7:0]
DQS[7:0]
EVENT
TEST
RESET
V
DD
V
SS
Description
Data Input/Output
Data Masks
Data strobes
Data strobes, negative line
Temperature event pin
Logic Analyzer specific test pin (No
connect on SODIMM)
Reset Pin
Core and I/O Power
Ground
Num
ber
64
8
8
8
1
1
1
18
52
Rev.1.3 /Sep. 2013
5
DSP and ARM Processors
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