MPC603PRX200L datasheet, PDF - EEWORLD Datasheet

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MPC603PRX200L: DescriptionRISC Microprocessor, 32-Bit, 200MHz, CMOS, CBGA255, 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255; CategoryThe embedded processor and controller Microcontrollers and processors; File Size157KB，40 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MPC603PRX200L Overview

RISC Microprocessor, 32-Bit, 200MHz, CMOS, CBGA255, 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255

MPC603PRX200L Parametric

Parameter Name	Attribute value
Maker	Motorola ( NXP )
package instruction	BGA,
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	200 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	NO
JESD-30 code	S-CBGA-B255
length	21 mm
low power mode	YES
Number of terminals	255
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	3 mm
speed	200 MHz
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	21 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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G522-0267-00

(IBM Order Number)

MPC603E7VEC/D

(Motorola Order Number)

11/96

REV 1

™

Advance Information

PowerPC 603e

™

RISC Microprocessor Family:

PID7v-603e Hardware Speciﬁcations

The PowerPC 603e microprocessor is an implementation of the PowerPC™ family of

reduced instruction set computing (RISC) microprocessors. In this document, the term

‘603e’ is used as an abbreviation for ‘PowerPC 603e microprocessor’. The PowerPC 603e

microprocessors are available from Motorola as MPC603e and from IBM as PPC603e.

Note that the 603e is implemented in both a 2.5-volt version (PID 0007v PowerPC 603e

microprocessor, abbreviated as PID7v-603e) and a 3.3-volt version (PID 0006 PowerPC

603e microprocessor, abbreviated as PID6-603e). This document describes the pertinent

physical characteristics of the PID7v-603e. For functional characteristics of the processor,

refer to the

PowerPC 603e RISC Microprocessor User’s Manual

This document contains the following topics:

Topic

Page

PID7v-603e Hardware Speciﬁcations

Section 1.1, “Overview”

Section 1.2, “Features”

Section 1.3, “General Parameters”

Section 1.4, “Electrical and Thermal Characteristics”

Section 1.5, “PowerPC 603e Microprocessor Pin Assignments”

Section 1.6, “PowerPC 603e Microprocessor Pinout Listings”

Section 1.7, “PowerPC 603e Microprocessor Package Descriptions”

Section 1.8, “System Design Information”

Section 1.9, “Ordering Information”

Appendix A, “General Handling Recommendations for the C4-CQFP Package”

The PowerPC name, the PowerPC logotype, PowerPC 603, and PowerPC 603e are trademarks of International Business Machines

Corporation, used by Motorola under license from International Business Machines Corporation.

This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to

change or discontinue this product without notice.

Portions hereof

To locate any published errata or updates for this document, refer to the website at http://www.mot.com/

powerpc/ or at http://www.chips.ibm.com/products/ppc.

1.1 Overview

This section describes the features of the 603e and describes brieﬂy how those units interact.

The 603e is a low-power implementation of the PowerPC microprocessor family of reduced instruction set

computing (RISC) microprocessors. The 603e implements the 32-bit portion of the PowerPC architecture

speciﬁcation, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and ﬂoating-

point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture provides

64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture.

The 603e provides four software controllable power-saving modes. Three of the modes (the nap, doze, and

sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor.

The fourth is a dynamic power management mode that causes the functional units in the 603e to

automatically enter a low-power mode when the functional units are idle without affecting operational

performance, software execution, or any external hardware.

The 603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock.

Instructions can execute out of order for increased performance; however, the 603e makes completion

appear sequential.

The 603e integrates ﬁve execution units—an integer unit (IU), a ﬂoating-point unit (FPU), a branch

processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute ﬁve

instructions in parallel and the use of simple instructions with rapid execution times yield high efﬁciency

and throughput for 603e-based systems. Most integer instructions execute in one clock cycle. The FPU is

pipelined so a single-precision multiply-add instruction can be issued every clock cycle.

The 603e provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches

for instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs

contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and

ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block

translation. The TLBs and caches use a least-recently used (LRU) replacement algorithm. The 603e also

supports block address translation through the use of two independent instruction and data block address

translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously

with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture,

if an effective address hits in both the TLB and BAT array, the BAT translation takes priority.

The 603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603e interface protocol allows

multiple masters to compete for system resources through a central external arbiter. The 603e provides a

three-state coherency protocol that supports the exclusive, modiﬁed, and invalid cache states. This protocol

is a compatible subset of the MESI (modiﬁed/exclusive/shared/invalid) four-state protocol and operates

coherently in systems that contain four-state caches. The 603e supports single-beat and burst data transfers

for memory accesses, and supports memory-mapped I/O.

The 603e uses an advanced, 2.5/3.3-V CMOS process technology and maintains full interface compatibility

with TTL devices.

PID7v-603e Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MPC603PRX200L Related Products

	MPC603PRX200L	MPC603PRX240L	MPC603PRX225L
Description	RISC Microprocessor, 32-Bit, 200MHz, CMOS, CBGA255, 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255	RISC Microprocessor, 32-Bit, 240MHz, CMOS, CBGA255, 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255	RISC Microprocessor, 32-Bit, 225MHz, CMOS, CBGA255, 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255
package instruction	BGA,	BGA,	BGA,
Reach Compliance Code	unknown	unknown	unknown
ECCN code	3A001.A.3	3A001.A.3	3A001.A.3
Address bus width	32	32	32
bit size	32	32	32
boundary scan	YES	YES	YES
maximum clock frequency	200 MHz	240 MHz	225 MHz
External data bus width	64	64	64
Format	FLOATING POINT	FLOATING POINT	FLOATING POINT
Integrated cache	NO	NO	NO
JESD-30 code	S-CBGA-B255	S-CBGA-B255	S-CBGA-B255
length	21 mm	21 mm	21 mm
low power mode	YES	YES	YES
Number of terminals	255	255	255
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA	BGA	BGA
Package shape	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3 mm	3 mm	3 mm
speed	200 MHz	240 MHz	225 MHz
Maximum supply voltage	2.625 V	2.625 V	2.625 V
Minimum supply voltage	2.375 V	2.375 V	2.375 V
Nominal supply voltage	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Terminal form	BALL	BALL	BALL
Terminal pitch	1.27 mm	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
width	21 mm	21 mm	21 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC
Maker	Motorola ( NXP )	-	Motorola ( NXP )

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