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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT841T/843T/845T
(25Ω
Series) PI74FCT2841T
Fast CMOS
Bus Interface Latches
Product Features
PI74FCT841/843/845/2841T is pin compatible with bipolar
FAST Series at a higher speed and lower power
consumption
25-ohm series resistor on all outputs (FCT2XXX only)
TTL input and output levels
Low ground bounce outputs
Extremely low static power
Hysteresis on all inputs
Industrial operating temperature range: 40°C to +85°C
Packages available:
24-pin 300 mil wide plastic DIP (P)
24-pin 150 mil wide plastic QSOP (Q)
24-pin 150 mil wide plastic TQSOP (R)
24-pin 300 mil wide plastic SOIC (S)
Product Description
Pericom Semiconductors PI74FCT series of logic circuits are
produced in the Companys advanced 0.8 micron CMOS technology,
achieving industry leading speed grades. All PI74FCT2XXX devices
have a built-in 25-ohm series resistor on all outputs to reduce noise
because of reflections, thus eliminating the need for an external
terminating resistor.
The PI74FCT841T/843T/845T and P174FCT2841T series are buffered
interface latches. These transparent latches designed with 3-state
outputs and are designed to eliminate the extra packages required to
buffer existing latches and provide extra data width for wider address/
data paths or buses carrying parity. When Latch Enable (LE) is HIGH,
the flip-flops appear transparent to the data. The data that meets the
set-up time when LE is LOW is latched. When OE is HIGH, the bus
output is in the high impedance state.
The PI74FCT841/2841T is a 10-bit latch, the PI74FCT843T is a
9-bit latch, and the PI74FCT845T is an 8-bit latch.
PI74FCT841/843/845/2842T Logic Block Diagram
D
0
PRE
D P
Q
LE
CLR
D P
LE Q
CLR
D P
LE Q
CLR
D P
LE Q
CLR
D P
LE Q
CLR
D P
LE Q
CLR
D P
LE Q
CLR
D P
LE Q
CLR
D
1
D
2
D
3
D
4
D
5
D
N–1
D
N
CLR
LE
OE
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
N–1
Y
N
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT841T/843T/845T
(25Ω
Series) P174FCT2841T
Bus Interface Latches
PI74FCT841/2841T 10-Bit Latch
Product Configuration
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
LE
Product Pin Description
Pin Name
Y
N
D
N
LE
OE
CLR
PRE
GND
V
CC
Description
3-State Latch Outputs
Latch Data Inputs
Latch Enable Input
Output Enable Control
Clear Latch
Preset Latch High, Preset Overrides CLR
Ground
Power
24-PIN
P24
Q24
R24
S24
PI74FCT843T 9-Bit Latch Product Configuration
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
CLR
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
Vcc
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
PRE
LE
Truth Table
(1)
Inputs
Outputs Internal
Function
High-Z
24-PIN
P24
Q24
R24
S24
21
20
19
18
17
16
15
14
13
CLR PRE OE
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
L
H
L
H
L
L
L
L
L
L
H
H
LE D
N
X X
H L
H H
L
H
H
L
X
X
X
L
L
X
L
H
X
X
X
X
X
X
Y
N
Z
Z
Z
Z
L
H
NC
H
L
H
Z
Z
Q
N
X
L
H
NC
L
H
NC
H
L
H
L
H
Latched
(High Z)
Transparent
Latched
Preset
Clear
Preset
Latched
(High Z)
Latched
(High Z)
1.
PI74FCT845T 8-Bit Latch Product Configuration
OE
1
OE
2
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CLR
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
OE
3
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
PRE
LE
24-PIN
P24
Q24
R24
S24
H = High Voltage Level
L = Low Voltage Level
X = Don't Care
NC = No Change
Z = High Impedance
2
PS2025A 03/11/96
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT841T/843T/845T
(25Ω
Series) P174FCT2841T
Bus Interface Latches
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................................................. 65°C to +150°C
Ambient Temperature with Power Applied ................................. -40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .......... 0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) ....... 0.5V to +7.0V
DC Input Voltage ......................................................................... 0.5V to +7.0V
DC Output Current ................................................................................... 120 mA
Power Dissipation ......................................................................................... 0.5W
Note:
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect reliability.
DC Electrical Characteristics
(Over the Operating Range, T
A
= 40°C to +85°C, V
CC
= 5.0V ± 5%)
Parameters Description
V
OH
V
OL
V
OL
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
OFF
I
OS
V
H
Output LOW Current
Output LOW Current
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
High Impedance
Output Current
Clamp Diode Voltage
Power Down Disable
Short Circuit Current
Input Hysteresis
V
CC
= Min., I
IN
= 18 mA
V
CC
= GND, V
OUT
= 4.5V
V
CC
= Max.
(3)
, V
OUT
= GND
60
Test Conditions
(1)
I
OH
= 15.0 mA
I
OL
= 48 mA
I
OL
= 12 mA (25Ω Series)
2.0
0.8
V
IN
= V
CC
V
IN
= GND
V
OUT
= 2.7V
V
OUT
= 0.5V
0.7
120
200
1
1
1
1
1.2
100
V
CC
= Min., V
IN
= V
IH
or V
IL
V
CC
= Min., V
IN
= V
IH
or V
IL
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= M
AX
.
Min. Typ
(2)
Max. Units
2.4
3.0
0.3
0.3
0.50
0.50
V
V
V
V
V
µA
µA
µA
µA
V
µA
mA
mV
Output HIGH Voltage V
CC
= Min., V
IN
= V
IH
or V
IL
Capacitance
(T
A
= 25°C, f = 1 MHz)
Parameters
(4)
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
6
8
Max.
10
12
Units
pF
pF
3
PS2025A 03/11/96
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PI74FCT841T/843T/845T
(25Ω
Series) P174FCT2841T
Bus Interface Latches
Power Supply Characteristics
Parameters Description
I
CC
∆I
CC
I
CCD
Quiescent Power
Supply Current
Supply Current per
Input @ TTL HIGH
Supply Current per
Input per MHz
(4)
V
CC
= Max.
V
CC
= Max.
V
CC
= Max.,
Outputs Open
OE = GND; LE = Vcc
One Input Toggling
50% Duty Cycle
V
CC
= Max.,
Outputs Open
f
CP
= 10 MH
Z
50% Duty Cycle
OE = GND; LE = Vcc
f
I
= 5 MH
Z
One Bit Toggling
V
CC
= Max.,
Outputs Open
f
CP
= 10 MH
Z
50% Duty Cycle
OE = GND; LE = Vcc
Eight Bits Toggling
f
I
= 2.5 MH
Z
50% Duty Cycle
Test Conditions
(1)
V
IN
= GND
or V
CC
V
IN
= 3.4V
(3)
V
IN
= V
CC
V
IN
= GND
Min.
Typ
(2)
0.1
0.5
0.15
Max.
500
2.0
0.25
Units
µA
mA
mA/
MHz
I
C
Total Power Supply
Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
1.5
1.8
3.5
(5)
4.5
(5)
mA
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
3.0
5.0
6.0
(5)
14.0
(5)
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. I
C
=I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
I
N
I
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
I
= Input Frequency
N
I
= Number of Inputs at f
I
All currents are in milliamps and all frequencies are in megahertz.
4
PS2025A 03/11/96
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT841T/843T/845T
(25Ω
Series) P174FCT2841T
Bus Interface Latches
PI74FCT841/2841T Switching Characteristics over Operating Range
841AT/2841AT
Com.
841BT/2841BT
Com.
Max
Min
Max
Min
841CT/2841CT
Com.
Max
Unit
Parameters
t
PLH
t
PHL
Description
Propagation Delay
D
N
to Y
N
(LE = HIGH)
Setup Time
Data to LE
Hold Time
Data to LE
Propagation Delay
LE to Y
N
Conditions
(1)
C
L
= 50 pF
R
L
= 500Ω
C
L
= 300 pF
(3)
R
L
= 500Ω
C
L
= 50 pF
R
L
= 500Ω
Min
1.5
1.5
2.5
2.5
9.0
8.0
12.0
16.0
10.0
23.0
7.0
8.0
1.5
1.5
2.5
2.5
1.5
4.0
1.5
1.5
1.5
1.5
6.5
13.0
8.0
15.5
8.0
14.0
6.0
7.0
1.5
1.5
2.5
2.5
1.5
4.0
1.5
1.5
1.5
1.5
5.5
13.0
6.4
15.0
6.5
12.0
5.7
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
SU
t
H
t
PLH
t
PHL
t
W
t
PZH
t
PZL
LE Pulse Width
(3)
(HIGH)
Output Enable Time
OE to Y
N
t
PHZ
t
PLZ
Output Disable Time
(3)
OE to Y
N
C
L
= 50 pF
R
L
= 500Ω
C
L
= 300 pF
(3)
R
L
= 500Ω
C
L
= 50 pF
R
L
= 500Ω
C
L
= 50 pF
R
L
= 500Ω
C
L
= 300 pF
(3)
R
L
= 500Ω
C
L
= 50 pF
R
L
= 500Ω
C
L
= 5 pF
(3)
R
L
= 500Ω
1.5
4.0
1.5
1.5
1.5
1.5
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
5
PS2025A 03/11/96
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