ZL40121
Low Power, Current Feedback
Dual Operational Amplifier
Data Sheet
Features
•
•
•
•
•
280MHz small signal bandwidth
1100V/µs slew rate
3.3mA/channel static supply current
60Mhz gain flatness to +/- 0.1dB
8 pin SOIC
Ordering Information
ZL40121/DCA
ZL40121/DCB
(tubes) 8 lead SOIC
(tape and reel) 8 lead SOIC
April 2003
-40°C to +85°C
The 280MHz Av=+1V/V small signal bandwidth and
1100V/µs slew rate make the device an excellent
solution for component video applications such as
driving RGB signals down significant cable lengths.
Other applications which may take advantage of the
ZL40121 dynamic performance features and matched
amplifiers include low cost high order active filters and
twisted pair driver/receivers.
Applications
•
•
•
•
•
Video switchers/routers
Video line drivers
Twisted pair driver/receiver
Active filters
Cable drivers
Description
The ZL40121 is a low power, dual, current feedback
operational amplifier offering high performance at a
low cost. The device provides a very high output
current drive capability of 65mA while requiring only
3.3mA of static supply current per channel. This
feature makes the ZL40121 the ideal choice where a
high density of high speed devices is required.
Out_1
1
8 V+
7 Out_2
In_n_1 2
1
In_p_1 3
6 In_n_2
2
V- 4
ZL40121
5 In_p_2
Figure 1 - Functional Block Diagram and Pin Connection
1
ZL40121
Application Notes
Current Feedback Op Amps
Current feedback op amps offer several advantages over voltage feedback amplifiers:
•
•
•
AC bandwidth not dependent on closed loop gain
High Slew Rate
Fast settling time
Data Sheet
The architecture of the current feedback opamp consists of a high impedance non-inverting input and a low
impedance inverting input which is always feedback connected. The error current is amplified by a transimpedance
amplifier which can be considered to have gain
Z
(
f
)
=
Z
o
f
1
+
j
f
o
where Z
o
is the DC gain.
It can be shown that the closed loop non-inverting gain is given by
Vout
=
Vin
Av
fR
f
1
+
j
f Z
o o
f
o
Z
o
GB
OL
=
R
f
R
f
where Av is the DC closed loop gain, R
f
is the feedback resistor. The closed loop bandwidth is therefore given by
BW
CL
=
and for low values of closed loop gain Av depends only on the feedback resistor R
f
and not the closed loop gain.
This can readily be seen from the performance characteristic frequency response graph with varying R
f
It can be shown that increasing the value of R
f
•
•
•
•
•
Increases closed loop stability
Decreases loop gain
Decreases bandwidth
Reduces gain peaking
Reduces overshoot
Using a resistor value of R
f
=510Ω for Av=+2 V/V gives good stability and bandwidth. However since requirements
for stability and bandwidth vary it may be worth some experimentation to find the optimal R
f
for a given application.
Layout Considerations
Correct high frequency operation requires a considered PCB layout as stray capacitances have a strong influence
over high frequency operation for this device. This is particularly important for high performance current feedback
opamps. The Zarlink evaluation board serves as a good example layout that should be copied. The following
guidelines should be followed:
•
•
•
Include 6.8uF tantalum and 0.1uF ceramic capacitors on both positive and negative supplies
Remove the ground plane under and around the part, especially near the input and output pins to reduce
parasitic capacitances
Minimize all trace lengths to reduce series inductance
2
Zarlink Semiconductor Inc.
Data Sheet
Application Diagrams
ZL40121
Vcc
6.8uF
•
•
•
Vin
0.1uF
•
½ ZL40121
•
Rf
Vout
Rin
•
Ra
•
0.1uF
•
6.8uF
Vee
•
Vout
Rf
=
Av
=
1
+
Vin
Ra
Figure 2 - Non-inverting Gain
•
Vcc
6.8uF
•
•
•
Rb
0.1uF
Vout
½ ZL40121
Vin
Rin
Rf
•
Ra
•
•
0.1uF
•
6.8uF
Vee
•
Vout
Rf
=
Av
= −
Vin
Ra
Figure 3 - Inverting Gain
Zarlink Semiconductor Inc.
3
ZL40121
Absolute Maximum Ratings
Parameter
1
2
Vin Differential
Output Short Circuit Protection
Symbol
V
IN
V
OS/C
Min
Max
±1.2
See Apps
Note in this
data sheet
±6.5
V-
V-
2
V+
V+
(see Note 3)
Data Sheet
Units
V
3
4
5
6
Supply voltage
Voltage at Input Pins
Voltage at Output Pins
EDS Protection
(HBM Human Body Model)
(see Note 2)
Storage Temperature
Latch-up test
Supply transient test
V+, V-
V
(+IN)
, V
(-IN)
V
O
V
V
V
kV
7
8
9
Note 1:
-55
+150
(see Note 4)
(see Note 5)
°C
±100
mA
for 100ms
20% pulse
for 100ms
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate
conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed
specifications and the test conditions, see the Electrical Characteristics.
Human body model, 1.5kΩ in series with 100pF. Machine model, 20Ωin series with 100pF.
0.8kV between the pairs of +INA, -INA and +INB pins only. 2kV between supply pins, OUTA or OUTB pins and any input pin.
±100mA applied to input and output pins to force the device to go into "latch-up". The device passes this test to JEDEC spec
17.
Positive and Negative supply transient testing increases the supplies by 20% for 100ms.
Note 2:
Note 3:
Note 4:
Note 5:
Operating Range
Characteristic
Supply Voltage (Vcc)
Operating Temperature (Ambient)
Junction to Ambient resistance
Min
±4.0
-40
Rth(j-a)
150
Typ
Max
Units
V
°C
°C
4 layer
FR4 board
°C
4 layer
FR4 board
Comments
±
6.0
+85
Junction to Case resistance
Rth(j-c)
60
4
Zarlink Semiconductor Inc.
Data Sheet
Rf=510Ω, Rload=100Ω unless specified
ZL40121
Electrical Characteristics -
Vcc=±5V, T
amb
=25C(typ.),T
amb
=-40C to +85C(min-max), Av=+2V/V,
Min
/Max
–40 to
+85C
Characteristic
Conditions
Typ
25C
Min/
Max
25C
Units
Test
Type
1
Frequency Domain Response
-3dB Bandwidth
Av=+1; Vo < 0.5Vp-p;
Rf=1.5kΩ
Av=+2; Vo < 0.5Vp-p;
Rf=510Ω
Av=+2; Vo < 5Vp-p;
Rf=510Ω
+/- 0.1dB Flatness
Differential Gain (NTSC)
Differential Phase (NTSC)
Time Domain Response
Rise and Fall Time
Vout=0.5V Step
Vout=5V Step
Settling Time to 0.1%
Overshoot
Slew Rate
Noise and Distortion
2
nd
Harmonic Distortion
3
nd
Harmonic Distortion
Equivalent Input Noise
Voltage
Non-Inverting Current
Inverting Current
>1MHz
>1MHz
>1MHz
6.4
1.0
9.3
-
-
-
-
-
-
Vout=2Vp-p, 1MHz
Vout=2Vp-p, 1MHz
-78
-88
-
-
-
-
dBc
dBc
C
C
1.4
3.6
6
6
1100
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
%
V/µs
C
C
C
C
C
280
230
130
60
0.02
0.06
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
%
deg.
C
C
C
C
C
C
Av=+2; Vo < 0.5Vp-p;
Rf=510Ω
Rload=150Ω
Rload=150Ω
Vout=2V Step
Vout=0.5V Step
Vout=5V Step
nV
Hz
pV
Hz
pA
Hz
C
C
C
Static, DC Performance
Input Offset Voltage
Average Drift
Input Bias Current – Non-inverting
Average Drift
1.4
-
1.3
-
± 6.0
-
±2.6
-
± 7.5
15
±2.8
2.6
mV
uV/deg. C
uA
nA/deg. C
A
C
A
C
Zarlink Semiconductor Inc.
5
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