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LDH65800PBAA-400

Description
Passive Delay Line, 1-Func, 0-Tap
Categorylogic    logic   
File Size198KB,11 Pages
ManufacturerMurata
Websitehttps://www.murata.com
Environmental Compliance  
Download Datasheet Parametric View All

LDH65800PBAA-400 Overview

Passive Delay Line, 1-Func, 0-Tap

LDH65800PBAA-400 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMurata
package instructionSON, SOLCC8,.2,20
Reach Compliance Codecompliant
JESD-30 codeR-XDSO-N6
JESD-609 codee4
Logic integrated circuit typePASSIVE DELAY LINE
Number of functions1
Number of taps/steps
Number of terminals6
Maximum operating temperature85 °C
Minimum operating temperature-25 °C
Output impedance nominal value (Z0)50 Ω
Package body materialUNSPECIFIED
encapsulated codeSON
Encapsulate equivalent codeSOLCC8,.2,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
programmable delay lineNO
Prop。Delay @ Nom-Sup0.9 ns
Certification statusNot Qualified
surface mountYES
Temperature levelOTHER
Terminal surfaceGOLD
Terminal formNO LEAD
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Total delay nominal (td)0.8 ns
Please read rating and
!CAUTION
(for storage, operating, rating, soldering, mounting and handling) in this catalog to prevent smoking and/or burning, etc.
!Note
•Please read rating and
!CAUTION
(for storage, operating, rating, soldering, mounting and handling) in this PDF catalog to prevent smoking and/or burning, etc.
•This catalog has only typical specifications. Therefore,thereareno space for detailed specifications. Therefore, please approve our productsheet for product specificaions approval sheet for product specifications before ordering.
This catalog has only typical specifications because you is requested to approve our product specifications or to transact the approval specifications or transact the before ordering.
N91E7.pdf 03.5.13
Chip Multilayer Delay Lines
Chip Multilayer Delay Lines
0.25+0.1/-0.15
3.2±0.2
1.1±0.2
0.5±0.1
1
This Delay Line was developed by applying ceramic
multilayering and hole technology. It consists of
copper line and low dielectric constant material and
incorporates metal shields. LDH series are very small
and made for use at high frequencies.
(3)
1.60±0.2
(4)
(2)
(1)
(8)
(5)
(6)
(7)
0.25+0.1/-0.15
0.35±0.2
0.45±0.15
(1)(3)(5)(7) : NC
(2)(6) : GND
(4)(8) : IN/OUT
s
Features
1. High stability at high frequency (2GHz)
2. Small, thin and light, utilizing multilayer
construction
3. Metal shield is built inside chip.
4. Reflow solderable
5. Supplied on tape
0.5±0.1
1.0±0.1
(in mm)
LDH31 Series
Terminal of "NC" should not be fixed to any pattern.
All the technical data and information contained herein are subject
to change without prior notice.
3.2±0.2
(3)
(2)
(1)
1.5±0.15
0.4±0.2 0.7±0.2
(4)
(8)
(5)
(6)
(7)
2.5±0.2
(1)(3)(5)(7) : NC
(2)(6) : GND
(4) : IN/OUT
(8) : IN/OUT
(in mm)
0.4±0.2
0.1min. 0.45±0.15 1.0±0.2
0.55±0.15
LDH32 Series
Terminal of "NC" should not be fixed
to any pattern.
All the technical data and information
contained herein are subject to
change without prior notice.
0.6±0.1
(1) (2)
(8)
(7) (6)
(3)
(4)
(5)
2.2±0.1
0.3±0.2
5.0±0.3
0.1±0.1
1.1–3.1
1.27±0.2
0.3max.
4.0±0.3
0.4±0.2
4.5±0.2
Directional
Input Mark
1.1±0.2
(6)
0.8±0.2
(5)
(4)
3.2±0.2
2.0±0.1
0.35±0.2
(1)(3)(4)(5)(7)(8) : GND
(2)(6)
: IN/OUT
1.27±0.2
LDH43 Series
0.35±0.10
(in mm)
All the technical data and information contained herein are
subject to change without prior notice.
1.27±0.10
LDH54 Series
0.3±0.2
(1)(3) : IN / OUT
(2) (4)
: GND
(5)(6)
(in mm)
6.3±0.3
2.5 max.
0.5 min.
1.27±0.2
0.5 min.
0.3 max.
6.3±0.3
(1) (2) (3) (4)
0.3±0.2
10.0±0.3
3.7 max.
0.4 min.
2.54±0.2
0.8 min.
0.3 max.
(1) (2) (3) (4)
(10)
(5)
0.4±0.2
0.9±0.3 3.0±0.3
(1)
(2)
(3)
5.0±0.3
2.1±0.3
0.55±0.3
0.5 min. 0.4 min.
(8) (7) (6) (5)
(9) (8) (7) (6)
1.4±0.3
0.55±0.3
(1) (5) : IN / OUT
(2)(3)(4) : GND
(6)(7)(8)
(in mm)
0.6 min. 0.4 min.
LDH65 Series
LDHA2 Series
(1) (6) : IN / OUT
(2)(3)(4) : GND
(5)(7)(8)
(9)(10)
(in mm)
Cat.No.N91E-7
1
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