4 Meg Based, 10 - 15ns, LP-STACK
30A236-04
A
4 Megabit 3.3 Volt High Speed SRAM
DP3S128X32Y5
ADVANCED INFORMATION
DESCRIPTION:
The DP3S128X32Y5 is the 128K x 32 SRAM module
the utilize the new and innovative space saving
TSOP stacking technology. The module is
constructed of four 128K x 8 SRAM’s that are
configured as 128K x 32.
The DP3S128X32Y5 provides for a compatible
upgrade path to lower density compatible modules.
The module features high speed access times with
common data inputs and outputs.
PIN NAMES
FEATURES:
•
Organizations Available:
128K x 32, 256K x 16 or 512K x 8
•
Access Times: 10, 12, 15ns
•
Fully Static Operation
- No clock or refresh required
•
Single +3.3V Power Supply, ±10% Tolerance
•
TTL Compatible
•
Common Data Inputs and Outputs
•
Package: 64-Pin TSOP Stack
PIN 1
INDEX
A0 - A16
I/O0 - I/O31
CE0 - CE3
WE
OE
V
DD
VSS
N.C.
Address
Data Input / Output
Low Chip Enables
Write Enable
Output Enable
Power (+3.3V)
Ground
No Connect
PIN-OUT DIAGRAM
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
47
A16
A15
OE
I/O7
I/O6
VSS
VDD
I/O5
I/O4
A14
A13
A12
A11
A10
A9
A8
(TOP VIEW)
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
FUNCTIONAL BLOCK DIAGRAM
CS0
I/O0
I/O\1
VDD
VSS
I/O2 10
I/O3 11
WE 12
A4 13
A5 14
A6 15
A7 16
30A236-04
REV. A
This document contains information on a product under consideration for
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right
to change or discontinue information on this product without prior notice.
1
DP3S128X32Y5
ADVANCED INFORMATION
RECOMMENDED OPERATING RANGE
3
Symbol
Characteristic
V
DD
Supply Voltage
V
IH
Input HIGH Voltage
V
IL
Input LOW Voltage
C
Operating
T
A
Temperature
CI
Min.
3.0
2.0
-0.3
2
0
-40
Typ.
3.3
Max. Unit
3.6
V
V
DD
+0.3 V
0.8
V
+25
+70
ºC
+25
+85
Mode
Not Selected
D
OUT
Disable
Read
Write
H = HIGH
Dense-Pac Microsystems, Inc.
TRUTH TABLE
CEn WE
H
L
L
L
OE
X
X
H
H
H
L
L
X
L = LOW
Supply
Current
HIGH-Z
Standby
HIGH-Z
Active
D
OUT
Active
D
IN
Active
X = Don’t Care
I/O Pin
CAPACITANCE
4
:
T
A
= +25ºC, F = 1.0MHz
Symbol
C
ADR
C
CE
C
WE
C
OE
C
I/O
Parameter
Address Input
Chip Enable
Write Enable
Output Enable
Data Input/Output
Max.
35
15
35
35
15
Unit Condition
ABSOLUTE MAXIMUM RATING
3
Symbol
T
STC
T
BIAS
V
DD
V
I/O
Parameter
Storage Temperature
Temperature Under Bias
Supply Voltage
1
Input/Output Voltage
1
Max.
-65 to +150
-55 to +125
-0.5 to +4.6
-0.5 to +4.6
Unit
ºC
ºC
V
V
pF
V
IN2
= 0V
DC OUTPUT CHARACTERISTICS
Symbol Parameter
Conditions Min. Max. Unit
V
OH
V
HIGH Voltage I
OH
= -4mA 2.4
V
OL
I
OL
=8mA
0.4
V
LOW Voltage
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
0V to 3.0V
5ns*
1.5V
319Ω
D
OUT
Figure 1.
Output Load
+3.3V
OUTPUT LOAD
Load
1
2
C
L
30pF
5pF
Parametric Measured
except t
LZ
, t
HZ
, t
OHZ
, t
OLZ
and t
WHZ
t
LZ
, t
HZ
, t
OHZ
, t
OLZ
and t
WHZ
C
L
*
353Ω
* Including Probe and Jig Capacitance.
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
V
OL
V
OH
DC OPERATING CHARACTERISTICS:
Over Operating Ranges
Characteristics
Min.
Test Condition
Input
Leakage Current
Output
Leakage Current
Operating
Supply Current
Full Standby
Standby Current
Standby Current (TTL)
Output LOW Voltage
Output HIGH Voltage
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD ,
CE or OE = V
IH
or WE = V
IL
Cycle = min., Duty = 100%,
I
OUT
= 0mA
V
IN
≥
V
DD
-0.2V or
V
IN
≤
V
SS
+0.2V
CE = V
IH
I
OL
= 8.0mA
I
OH
= -4.0mA
X8
X16
X32
-8
-2
Max.
+8
+2
355
450
640
180
260
0.4
Unit
µA
µA
mA
mA
mA
V
V
2.4
Note:
Typical measurements made at +25°C. Cycle = min., V
DD
= 5.0V.
2
30A236-04
REV. A
Dense-Pac Microsystems, Inc.
ADVANCED INFORMATION
DP3S128X32Y5
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
No.
1
2
3
4
5
6
7
8
9
Symbol
t
RC
t
AA
t
CO
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
Parameter
Read Cycle Time
Address Cycle Time
Chip Enable Access Time
Output Enable to Output Valid
Chip Enable to Output in LOW-Z
4, 6
Output Enable to Output in LOW-Z
Chip Enable to Output in HIGH-Z
Output Enable to Output in HIGH-Z
Output Hold from Address Change
4, 5
4, 5
4, 5
10ns
Min.
Max.
12ns
Min.
Max.
Over Operating Ranges
15ns
Unit
Min.
Max.
10
10
10
5
3
0
0
0
3
5
5
12
12
12
6
3
0
0
0
3
6
6
15
15
15
7
3
0
0
0
3
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC OPERATING CONDITION AND CHARACTERISTIC READ CYCLE:
Over Operating Ranges
No.
10
11
12
13
14
15
16
17
18
19
20
Symbol
t
WC
t
AW
t
CW
t
SA
t
WP
t
WP1
t
WR
t
WHZ
t
DW
t
DH
t
OW
Parameter
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Setup Time *
Write Pulse Width (OE High)
Write Pulse Width (OE Low)
Write Recovery Time
Write Enable to Output in HIGH
Data to Write Time Overlap
Data Hold Time form Write Time
Output Active from End of Write
4, 5
4, 5
6, 7
10ns
Min.
Max.
12ns
Min.
Max.
15ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
10
8
8
0
8
10
0
0
6
0
3
5
12
9
9
0
9
12
0
0
6
0
3
6
15
10
10
0
10
14
0
0
7
0
3
7
ns
ns
ns
ns
* Valid for both Read and Write Cycles.
READ CYCLE 1:
Address Controlled WE is HIGH CE and OE are LOW.
ADDRESS
DATA I/O
30A236-04
REV. A
3
DP3S128X32Y5
ADVANCED INFORMATION
Dense-Pac Microsystems, Inc.
READ CYCLE 2:
CE is Controlled. WE is HIGH.
ADDRESS
CE
OE
DATA I/O
WRITE CYCLE 1:
OE Clock.
ADDRESS
CE
CE
WE
DATA IN
DATA OUT
4
30A236-04
REV. A
Dense-Pac Microsystems, Inc
.
ADVANCED INFORMATION
DP3S128X32Y5
WRITE CYCLE 2:
OE is LOW.
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 3:
CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
30A236-04
REV. A
5
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