QS5993-2TQ datasheet, PDF - EEWORLD Datasheet

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QS5993-2TQ: DescriptionClock Driver, CMOS, PDSO28; Categorylogic logic; File Size116KB，8 Pages; ManufacturerIDT (Integrated Device Technology)

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QS5993-2TQ Overview

Clock Driver, CMOS, PDSO28

QS5993-2TQ Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Reach Compliance Code	not_compliant
JESD-30 code	R-PDSO-G28
JESD-609 code	e0
MaximumI(ol)	0.046 A
Humidity sensitivity level	1
Number of terminals	28
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SSOP28,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Prop。Delay @ Nom-Sup	0.25 ns
Certification status	Not Qualified
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	6

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QS5993

PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

PROGRAMMABLE SKEW

PLL CLOCK DRIVER

TURBOCLOCK™

FEATURES:

•

3 pairs of programmable skew outputs

Low skew: 200ps same pair, 250ps all outputs

Selectable positive or negative edge synchronization:

Excellent for DSP applications

Synchronous output enable

Output frequency: 6.25MHz to 100MHz

2x, 4x, 1/2, and 1/4 outputs

5V with TTL outputs

3 skew grades:

QS5993-2: t

SKEW0

<250ps

QS5993-5: t

SKEW0

<500ps

QS5993-7: t

SKEW0

<750ps

3-level inputs for skew and PLL range control

PLL bypass for DC testing

External feedback, internal loop filter

46mA I

high drive outputs

Low Jitter: <200ps peak-to-peak

Outputs drive 50Ω terminated lines

Available in QSOP Package

QS5993

DESCRIPTION:

The QS5993 is a high fanout PLL based clock driver intended for

high performance computing and data-communications applications. A

key feature of the programmable skew is the ability of outputs to lead or

lag the REF input signal. The QS5993 has six programmable skew

outputs and two zero skew outputs. Skew is controlled by 3-level input

signals that may be hard-wired to appropriate HIGH-MID-LOW levels.

•

FUNCTIONAL BLOCK DIAGRAM

G ND/sOE

Skew

Select

1F1:0

CCQ

/PE

Skew

Select

REF

PLL

Skew

Select

3F1:0

2F1:0

COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES

2000

Integrated Device Technology, Inc.

MARCH 2000

DSC-5811/-

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