5AGXMA1D431I4N datasheet, PDF - EEWORLD Datasheet

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5AGXMA1D431I4N: DescriptionFPGA, 670 MHz, PBGA1152; Categorysemiconductor Programmable logic devices; File Size772KB，37 Pages; ManufacturerAltera (Intel)

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5AGXMA1D431I4N Overview

FPGA, 670 MHz, PBGA1152

5AGXMA1D431I4N Parametric

Parameter Name	Attribute value
Number of terminals	1152
Processing package description	ROHS COMPLIANT, FBGA-1152
state	Active
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
clock_frequency_max	670 MHz
jesd_30_code	S-PBGA-B1152
Packaging Materials	PLASTIC/EPOXY
ckage_code	BGA
packaging shape	SQUARE
Package Size	GRID ARRAY
seated_height_max	2.7 mm
Rated supply voltage	1.15 V
Minimum supply voltage	1.12 V
Maximum supply voltage	1.18 V
surface mount	YES
Terminal form	BALL
Terminal spacing	1 mm
Terminal location	BOTTOM
length	35 mm
width	35 mm

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Arria V Device Overview

2013.05.06

AV-51001

Feedback

The Arria

V device family consists of the most comprehensive offerings of mid-range FPGAs ranging from

the lowest power for 6 gigabits per second (Gbps) and 10 Gbps applications, to the highest mid-range FPGA

bandwidth 12.5 Gbps transceivers.

The Arria V devices are ideal for power-sensitive wireless infrastructure equipment, 20G/40G bridging,

switching, and packet processing applications, high-definition video processing and image manipulation,

and intensive digital signal processing (DSP) applications.

Related Information

Arria V Device Handbook: Known Issues

Lists the planned updates to the

Arria V Device Handbook

chapters.

Key Advantages of Arria V Devices

Table 1: Key Advantages of the Arria V Device Family

Advantage

Supporting Feature

Lowest static power in its class • Built on TSMC's 28 nm process technology and includes an abundance of

hard intellectual property (IP) blocks

• Power-optimized MultiTrack routing and core architecture

• Up to 50% lower power consumption than the previous generation device

• Lowest power transceivers of any midrange family

Improved logic integration and • 8-input adaptive logic module (ALM)

differentiation capabilities

• Up to 38.38 megabits (Mb) of embedded memory

• Variable-precision digital signal processing (DSP) blocks

Increased bandwidth capacity • Serial data rates up to 12.5 Gbps

• Hard memory controllers

Hard processor system (HPS) • Tight integration of a dual-core ARM Cortex-A9 MPCore processor, hard

with integrated ARM

IP, and an FPGA in a single Arria V system-on-a-chip (SoC) FPGA

™

Cortex -A9 MPCore processor • Supports over 128 Gbps peak bandwidth with integrated data coherency

between the processor and the FPGA fabric

words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words

and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.

Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the

right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application

or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to

obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

www.altera.com

101 Innovation Drive, San Jose, CA 95134

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