WF4M32-XXX5
4Mx32 5V NOR FLASH MODULE
FEATURES
Access Times of 100, 120, 150ns
Packaging:
• 66 pin, PGA Type, 1.385" square, Hermetic Ceramic HIP
(Package 402).
• 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square
(Package 509) 4.57mm (0.180") height. Designed to fit
JEDEC 68 lead 0.990CQFJ footprint (Fig. 3)
Sector Architecture
• 32 equal size sectors of 64KBytes per each 2Mx8 chip
• Any combination of sectors can be erased. Also supports
full chip erase.
Minimum 100,000 Write/Erase Cycles Minimum
Organized as 4Mx32
User configurable as 2x4Mx16 or 4x4Mx8 in HIP.
Commercial, Industrial, and Military Temperature Ranges
* This product is subject to change without notice.
Note: For programming information refer to Flash Programming 16M5 Application Note.
5 Volt Read and Write. 5V ± 10% Supply.
Low Power CMOS
Data# Polling and Toggle Bit feature for detection of
program or erase cycle completion.
Supports reading or programming data to a sector not being
erased.
RESET# pin resets internal state machine to the read
mode.
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation, Separate Power and Ground Planes to
improve noise immunity
FIGURE 1 – PIN CONFIGURATION FOR
WF4M32-XH2X5
Top View
1
I/O
8
I/O
9
I/O
10
A
14
A
16
A
11
A
0
A
18
I/O
0
I/O
1
I/O
2
11
22
12
RESET#
PIN DESCRIPTION
I/O
0-31
A
0-21
WE#
CS
1-4
#
OE#
V
CC
V
SS
RESET#
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Reset
23
I/O
15
I/O
14
I/O
13
I/O
12
OE#
A
17
WE#
I/O
7
I/O
6
I/O
5
I/O
4
33
I/O
24
I/O
25
I/O
26
A
7
A
12
A
21
A
13
A
8
I/O
16
I/O
17
I/O
18
34
V
CC
CS
4#
NC
I/O
27
A
4
A
5
A
6
A20
CS
3#
GND
I/O
19
44
45
I/O
31
I/O
30
I/O
29
I/O
28
A
1
A
2
56
CS
2#
GND
I/O
11
A
10
A
9
A
15
V
CC
CS
1#
A
19
I/O
3
BLOCK DIAGRAM
CS1#
A
21
CS2#
CS3#
CS4#
A
3
I/O
23
OE#
I/O
22
I/O
21
I/O
20
55
66
WE#
A
0-20
RESET#
2M x 8
2M x 8
2Mx 8
2M x 8
2M
x 8
2M
x 8
2M
x 8
2M
x 8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011
Rev. 9
© 2011 Microsemi Corporation. All rights reserved.
1
Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
www.microsemi.com
WF4M32-XXX5
FIGURE 2 – PIN CONFIGURATION FOR WF4M32-XG2TX5
PIN DESCRIPTION
TOP VIEW
RESET#
A
0
A
1
A
2
A
3
A
4
A
5
NC
GND
NC
WE#
A
6
A
7
A
8
A
9
A
10
V
CC
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A
11
A
12
A
13
A
14
A
15
A
16
CS
1
#
OE#
CS
2
#
A
17
NC
NC
NC
V
CC
A
18
A
19
A
20
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
I/O
0-31
A
0-21
WE#
CS
1-2
#
OE#
V
CC
GND
RESET#
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Reset
Block Diagram
CS
1 #
RESET#
WE#
OE#
A
0-20
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
8
8
8
8
CS
2 #
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
Note: CS1#& CS2# are used as bank select
The White 68 lead G2T CQFP
fi
lls the same
fi
t and function
as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has
the TCE and lead inspection advantage of the CQFP form.
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011
Rev. 9
© 2011 Microsemi Corporation. All rights reserved.
2
Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
www.microsemi.com
WF4M32-XXX5
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on Any Pin Relative to V
SS
Power Dissipation
Storage Temperature
Short Circuit Output Current
Endurance — write/erase cycles
Data Retention (Mil Temp)
CAPACITANCE
Unit
V
W
°C
mA
cycles
years
Symbol
V
T
P
T
T
STG
I
OS
(Mil Temp)
Ratings
-2.0 to +7.0
8
-65 to +125
100
100,000 min.
20
T
A
= +25°C, V
IN
= OV,
F
= 1.0MHz
Parameter
OE# capacitance
WE# capacitance
CS# capacitance
Data I/O capacitance
Address input capacitance
Symbol
C
OE
C
WE
C
CS
C
I/O
C
AD
HIP (H2)
75
75
20
30
75
CQFP (G2T) CQFP(G4T)
75
75
50
30
75
20
20
20
30
20
This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Operating Temperature (Mil.)
Operating Temperature (Ind.)
Symbol
V
CC
V
SS
V
IH
V
IL
T
A
T
A
Min
4.5
0
2.0
-0.5
-55
-40
Typ
5.0
0
–
–
–
–
Max
5.5
0
V
CC
+ 0.5
+0.8
+125
+85
Unit
V
V
V
V
°C
°C
DC CHARACTERISTICS – CMOS COMPATIBLE
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
HIP
Parameter
Input Leakage Current
Output Leakage Current
V
CC
Active Current for Read (1)
V
CC
Active Current for Program or Erase (2)
V
CC
Standby Current
Output Low Voltage
Output High Voltage
Low V
CC
Lock-Out Voltage
Symbol
I
LI
I
LOX32
I
CC1
I
CC2
I
CC3
V
OL
V
OH
V
LKO
2.
3.
G2T
Max
10
10
320
420
20
0.45
Min
Max
10
10
215
295
2.0
0.45
0.85 x
V
CC
3.2
0.85 x
V
CC
3.2
Min
G4T
Max
10
10
345
445
95
0.45
Unit
μA
μA
mA
mA
mA
V
V
V
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
V
CC
= 5.5, V
IN
= GND to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz
CS# = V
IL
, OE# = V
IH
V
CC
= 5.5, CS# = V
IH
,
f = 5MHz, RESET# = V
IH
I
OL
= 12.0 mA, V
CC
= 4.5
I
OH
= -2.5 mA, V
CC
= 4.5
Min
0.85 x
V
CC
3.2
4.2
4.2
4.2
NOTES:
1. The I
CC
current listed includes both the DC operating current and the frequency dependent
component (@ 5MHz). The frequency component typically is less than 2mA/MHz, with OE# at
V
IH
.
I
CC
active while Embedded Algorithm (program or erase) is in progress.
DC test conditions V
IL
= 0.3V, V
IH
= V
CC
- 0.3V
HIP = 66 pin, PGA Type, 1.385" square, Hermetic Ceramic HIP (Package 402).
G2T = 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square. Designed to
fi
t JEDEC 68
lead 0.990" CQFJ footprint (Fig. 3) (Package 509)
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011
Rev. 9
© 2011 Microsemi Corporation. All rights reserved.
3
Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
www.microsemi.com
WF4M32-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - WE# CONTROLLED
V
CC
= 5.0V, -55°C
≤
T
A
≤
+125°C
Parameter
Write Cycle Time
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase (2)
Read Recovery Time before Write
V
CC
Setup Time
Chip Programming Time
Chip Erase Time (3)
Output Enable Hold Time (4)
RESET# Pulse Width
NOTES:
1. Typical value for tWHWH1 is 7μs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
Symbol
t
AVAV
t
ELWL
t
WLWH
t
AVWL
t
DVWH
t
WHDX
t
WLAX
t
WHWL
t
WHWH1
t
WHWH2
t
GHWL
t
VCS
t
WC
t
CS
t
WP
t
AS
t
DS
t
DH
t
AH
t
WPH
Min
100
0
45
0
45
0
45
20
-100
Max
Min
120
0
50
0
50
0
50
20
-120
Max
Min
150
0
50
0
50
0
50
20
-150
Max
300
15
0
50
44
256
t
OEH
t
RP
10
500
10
500
0
50
300
15
0
50
44
256
10
500
300
15
44
256
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
sec
μs
μs
sec
sec
ns
ns
AC CHARACTERISTICS – READ-ONLY OPERATIONS
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select High to Output High Z (1)
Output Enable High to Output High Z (1)
Output Hold from Addresses, CS# or OE# Change,
whichever is First
RESET# Low to Read Mode (1)
1.
Guaranteed by design, not tested.
T
AVAV
T
AVQV
T
ELQV
T
GLQV
T
EHQZ
T
GHQZ
T
AXQX
Symbol
T
RC
T
ACC
T
CE
T
OE
T
DF
T
DF
T
OH
T
READY
Min
100
-1000
Max
100
100
40
20
20
Min
120
-120
Max
120
120
50
30
30
Min
150
-150
Max
150
150
55
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
0
20
0
20
0
20
μs
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011
Rev. 9
© 2011 Microsemi Corporation. All rights reserved.
4
Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
www.microsemi.com
WF4M32-XXX5
AC CHARACTERISTICS FOR G2T PACKAGE – WRITE/ERASE/PROGRAM OPERATIONS,
CS# CONTROLLED
V
CC
= 5.0V, GND = 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Write Cycle Time
Write Enable Setup Time
Chip Select Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Chip Select Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time
Chip Programming Time
Chip Erase Time (3)
Output Enable Hold Time (4)
NOTES:
1. Typical value for t
WHWH1
is 7μs.
2. Typical value for t
WHWH2
is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
Symbol
t
AVAV
t
WLEL
t
ELEH
t
AVEL
t
DVEH
t
EHDX
t
ELAX
t
EHEL
t
WHWH1
t
WHWH2
t
GHEL
t
WC
t
WS
t
CP
t
AS
t
DS
t
DH
t
AH
t
CPH
Min
100
0
45
0
45
0
45
20
-100
Max
Min
120
0
50
0
50
0
50
20
-120
Max
Min
150
0
50
0
50
0
50
20
-150
Max
300
15
0
44
256
t
OEH
10
10
300
15
0
44
256
10
300
15
0
44
256
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
sec
μs
sec
sec
ns
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011
Rev. 9
© 2011 Microsemi Corporation. All rights reserved.
5
Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
www.microsemi.com
京公网安备 11010802033920号
EEWORLD
