Datasheet
μ
PD46185084B
μ
PD46185094B
μ
PD46185184B
μ
PD46185364B
18M-BIT QDR II SRAM
4-WORD BURST OPERATION
Description
The
μ
PD46185084B is a 2,097,152-word by 8-bit, the
μ
PD46185094B is a 2,097,152-word by 9-bit, the
μ
PD46185184B is a 1,048,576-word by 18-bit and the
μ
PD46185364B is a 524,288-word by 36-bit synchronous
quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory
cell.
The
μ
PD46185084B,
μ
PD46185094B,
μ
PD46185184B and
μ
PD46185364B integrate unique synchronous
peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are
latched on the positive edge of K and K#. These products are suitable for application which require
synchronous operation, high speed, low voltage, high density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
TM
R10DS0113EJ0200
Rev.2.00
Nov 09, 2012
Features
•
1.8 ± 0.1 V power supply
•
165-pin PLASTIC BGA (13 x 15)
•
HSTL interface
•
PLL circuitry for wide output data valid window and future frequency scaling
•
Separate independent read and write data ports with concurrent transactions
•
100% bus utilization DDR READ and WRITE operation
•
Four-tick burst for reduced address frequency
•
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
•
Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
•
Internally self-timed write control
•
Clock-stop capability. Normal operation is restored in 20
μ
s after clock is resumed.
•
User programmable impedance output (35 to 70
Ω)
•
Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz)
•
Simple control logic for easy depth expansion
•
JTAG 1149.1 compatible test access port
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 1 of 38
μ
PD46185084B,
μ
PD46185094B,
μ
PD46185184B,
μ
PD46185364B
Ordering Information
Organization
Part No.
(word x bit)
2M x 8
2M x 9
1M x 18
512K x 36
2M x 8
2M x 9
1M x 18
512K x 36
2M x 8
2M x 9
1M x 18
512K x 36
2M x 8
2M x 9
1M x 18
512K x 36
Cycle
time
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
Clock
frequency
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
Core
Supply
Voltage
1.8
±
0.1 V
Operating
Ambient
Temperature
T
A
= 0 to 70°C
Package
165-pin
PLASTIC
BGA
(13 x 15)
Lead-free
μ
PD46185084BF1-E33-EQ1-A
μ
PD46185084BF1-E40-EQ1-A
μ
PD46185094BF1-E33-EQ1-A
μ
PD46185094BF1-E40-EQ1-A
μ
PD46185184BF1-E33-EQ1-A
μ
PD46185184BF1-E40-EQ1-A
μ
PD46185364BF1-E33-EQ1-A
μ
PD46185364BF1-E40-EQ1-A
μ
PD46185084BF1-E33Y-EQ1-A
μ
PD46185084BF1-E40Y-EQ1-A
μ
PD46185094BF1-E33Y-EQ1-A
μ
PD46185094BF1-E40Y-EQ1-A
μ
PD46185184BF1-E33Y-EQ1-A
μ
PD46185184BF1-E40Y-EQ1-A
μ
PD46185364BF1-E33Y-EQ1-A
μ
PD46185364BF1-E40Y-EQ1-A
μ
PD46185084BF1-E33-EQ1
μ
PD46185084BF1-E40-EQ1
μ
PD46185094BF1-E33-EQ1
μ
PD46185094BF1-E40-EQ1
μ
PD46185184BF1-E33-EQ1
μ
PD46185184BF1-E40-EQ1
μ
PD46185364BF1-E33-EQ1
μ
PD46185364BF1-E40-EQ1
μ
PD46185084BF1-E33Y-EQ1
μ
PD46185084BF1-E40Y-EQ1
μ
PD46185094BF1-E33Y-EQ1
μ
PD46185094BF1-E40Y-EQ1
μ
PD46185184BF1-E33Y-EQ1
μ
PD46185184BF1-E40Y-EQ1
μ
PD46185364BF1-E33Y-EQ1
μ
PD46185364BF1-E40Y-EQ1
1.8
±
0.1 V
T
A
=
−40
to 85°C
1.8
±
0.1 V
T
A
= 0 to 70°C
165-pin
PLASTIC
BGA
(13 x 15)
Lead
1.8
±
0.1 V
T
A
=
−40
to 85°C
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 2 of 38
μ
PD46185084B,
μ
PD46185094B,
μ
PD46185184B,
μ
PD46185364B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD46185084B]
2M x 8
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/72M
3
A
NC
NC
NC
Q4
NC
Q5
V
DD
Q
NC
NC
D6
NC
NC
Q7
A
4
W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
NW1#
NC/288M
6
K#
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC/144M
8
R#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
V
SS
/36M
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
NW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
A
D0 to D7
Q0 to Q7
R#
W#
NW0#, NW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Nibble Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1.
×××#
indicates active LOW.
2.
Refer to
Package Dimensions
for the index mark.
3.
2A, 7A, 10A and 5B are expansion addresses : 10A for 36Mb
: 10A and 2A for 72Mb
: 10A, 2A and 7A for 144Mb.
: 10A, 2A, 7A and 5B for 288Mb.
2A and 10A of this product can also be used as NC.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 3 of 38
μ
PD46185084B,
μ
PD46185094B,
μ
PD46185184B,
μ
PD46185364B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD46185094B]
2M x 9
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/72M
3
A
NC
NC
NC
Q5
NC
Q6
V
DD
Q
NC
NC
D7
NC
NC
Q8
A
4
W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
NC
NC/288M
6
K#
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC/144M
8
R#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
V
SS
/36M
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
NC
NC
D5
NC
NC
D6
V
REF
NC
NC
Q7
NC
D8
NC
TCK
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
NC
NC
NC
D3
NC
NC
V
REF
Q2
NC
NC
NC
NC
D0
TMS
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
A
D0 to D8
Q0 to Q8
R#
W#
BW0#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1.
×××#
indicates active LOW.
2.
Refer to
Package Dimensions
for the index mark.
3.
2A, 7A, 10A and 5B are expansion addresses : 10A for 36Mb
: 10A and 2A for 72Mb
: 10A, 2A and 7A for 144Mb
: 10A, 2A, 7A and 5B for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 4 of 38
μ
PD46185084B,
μ
PD46185094B,
μ
PD46185184B,
μ
PD46185364B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD46185184B]
1M x 18
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
3
4
W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
BW1#
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K#
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC/288M
8
R#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
V
SS
/72M
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
V
SS
/144M NC/36M
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
D9
D10
Q10
Q11
D12
Q13
V
DD
Q
D14
Q14
D15
D16
Q16
Q17
A
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
A
D0 to D17
Q0 to Q17
R#
W#
BW0#, BW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1.
×××#
indicates active LOW.
2.
Refer to
Package Dimensions
for the index mark.
3.
2A, 3A, 7A and 10A are expansion addresses : 3A for 36Mb
: 3A and 10A for 72Mb
: 3A, 10A and 2A for 144Mb
: 3A, 10A, 2A and 7A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 5 of 38
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