Low-Cost 8-bit MCU Family with up to 8 kB of Flash
Memory
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Up to 8 kB flash
-
Flash is in-system programmable in 512-Byte sectors
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Up to 512 Bytes RAM (256 + 256)
On-Chip Debug
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On-chip debug circuitry facilitates full speed, non-intrusive in-
-
system debug (no emulator required)
Provides breakpoints, single stepping, inspect/modify memory
and registers
C8051F85x/86x
High-Speed CIP-51 µC Core
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Efficient, pipelined instruction architecture
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Up to 25 MIPS throughput with 25 MHz clock
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Uses standard 8051 instruction set
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Expanded interrupt handler
General-Purpose I/O
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Up to 18 pins
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5 V-Tolerant
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Crossbar-enabled
Communication Peripherals
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UART
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I
2
C / SMBus™
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SPI™
Timer/Counters and PWM
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4 General-Purpose 16-bit Timer/Counters
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16-bit Programmable Counter Array (PCA) with three channels
of PWM, capture/compare, or frequency output capability, and
hardware kill/safe state capability
12-Bit Analog-to-Digital Converter
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Up to 16 input channels
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Up to 200 ksps 12-bit mode or 800 ksps 10-bit mode
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Internal VREF or external VREF supported
Internal Low-Power Oscillator
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Calibrated to 24.5 MHz
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Low supply current
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±2% accuracy over supply and temperature
Internal Low-Frequency Oscillator
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80 kHz nominal operation
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Low supply current
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Independent clock source for watchdog timer
2 Analog Comparators
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Programmable hysteresis and response time
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Configurable as interrupt or reset source
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Low current
Additional Support Peripherals
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Independent watchdog timer clocked from LFO
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16-bit CRC engine
Core / Memory / Support
2-8 kB Flash
256-512 B RAM
Watchdog
CIP-51
(25 MHz)
Core LDO
Supply Monitor
16-bit CRC
Supply Voltage
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2.2 to 3.6 V
Package Options
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16-pin SOIC
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20-pin QFN, 3 x 3 mm
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24-pin QSOP
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Available in die form
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Qualified to AEC-Q100 Standards
Temperature Ranges:
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–40 to +125 °C (-Ix) and –40 to +85 °C (-Gx)
Digital Peripherals
18 Multi-Function 5V-Tolerant I/O Pins
UART
I2C / SMBus
SPI
4 x 16-bit Timers
3-Channel PCA
Priority Crossbar
Encoder
Flexible Pin Muxing
C2 Serial Debug / Programming
24.5 MHz Low Power Oscillator
80 kHz Low Frequency Oscillator
External Clock (CMOS Input)
Clock Selection
Clocking / Oscillators
Analog Peripherals
SAR ADC
(12-bit 200 ksps,10-bit 800 ksps)
Voltage Reference
2 x Low Current Comparators
Preliminary Rev 0.6 7/13
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Copyright © 2013 by Silicon Laboratories
C8051F85x/86x
C8051F85x/86x
Ta ble of Contents
1. Electrical Specifications......................................................................................................7
1.1. Electrical Characteristics ................................................................................................7
1.2. Typical Power Curves .................................................................................................. 17
1.2.1. Operating Supply Current .................................................................................... 17
1.2.2. ADC Supply Current ............................................................................................ 18
1.3. Thermal Conditions ...................................................................................................... 19
1.4. Absolute Maximum Ratings..........................................................................................19
2. System Overview ...............................................................................................................20
2.1. Power ........................................................................................................................... 22
2.1.1. LDO .................................................................................................................. 22
2.1.2. Voltage Supply Monitor (VMON0) ....................................................................... 22
2.1.3. Device Power Modes........................................................................................... 22
2.2. I/O................................................................................................................................. 23
2.2.1. General Features.................................................................................................23
2.2.2. Crossbar .............................................................................................................. 23
2.3. Clocking........................................................................................................................ 24
2.4. Counters/Timers and PWM ..........................................................................................24
2.4.1. Programmable Counter Array (PCA0) ................................................................. 24
2.4.2. Timers (Timer 0, Timer 1, Timer 2 and Timer 3).................................................. 24
2.4.3. Watchdog Timer (WDT0)..................................................................................... 24
2.5. Communications and other Digital Peripherals ............................................................ 25
2.5.1. Universal Asynchronous Receiver/Transmitter (UART0) .................................... 25
2.5.2. Serial Peripheral Interface (SPI0) ........................................................................ 25
2.5.3. System Management Bus / I2C (SMBus0) .......................................................... 25
2.5.4. 16/32-bit CRC (CRC0)......................................................................................... 25
2.6. Analog Peripherals ....................................................................................................... 26
2.6.1. 12-Bit Analog-to-Digital Converter (ADC0) .......................................................... 26
2.6.2. Low Current Comparators (CMP0, CMP1) .......................................................... 26
2.7. Reset Sources..............................................................................................................27
2.8. On-Chip Debugging...................................................................................................... 27
3. Pin Definitions.................................................................................................................... 28
3.1. C8051F850/1/2/3/4/5 QSOP24 Pin Definitions ............................................................ 28
3.2. C8051F850/1/2/3/4/5 QFN20 Pin Definitions ............................................................... 31
3.3. C8051F860/1/2/3/4/5 SOIC16 Pin Definitions..............................................................34
4. Ordering Information .........................................................................................................37
5. QSOP-24 Package Specifications .................................................................................... 39
6. QFN-20 Package Specifications ....................................................................................... 41
7. SOIC-16 Package Specifications ...................................................................................... 44
8. Memory Organization ........................................................................................................46
8.1. Program Memory.......................................................................................................... 47
8.1.1. MOVX Instruction and Program Memory............................................................. 47
8.2. Data Memory................................................................................................................ 47
8.2.1. Internal RAM........................................................................................................47
8.2.2. External RAM....................................................................................................... 48
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Preliminary Rev 0.6
C8051F85x/86x
8.2.3. Special Function Registers .................................................................................. 48
9. Special Function Register Memory Map.......................................................................... 49
10. Flash Memory..................................................................................................................... 54
10.1.Security Options........................................................................................................... 54
10.2.Programming The Flash Memory ................................................................................ 56
10.2.1.Flash Lock and Key Functions ............................................................................56
10.2.2.Flash Erase Procedure........................................................................................ 56
10.2.3.Flash Write Procedure......................................................................................... 56
10.3.Non-volatile Data Storage............................................................................................ 57
10.4.Flash Write and Erase Guidelines ............................................................................... 57
10.4.1.Voltage Supply Maintenance and the Supply Monitor.........................................57
10.4.2.PSWE Maintenance ............................................................................................ 57
10.4.3.System Clock....................................................................................................... 58
10.5.Flash Control Registers ............................................................................................... 59
11. Device Identification .......................................................................................................... 62
11.1.Device Identification Registers..................................................................................... 62
12. Interrupts ............................................................................................................................ 65
12.1.MCU Interrupt Sources and Vectors ............................................................................65
12.1.1.Interrupt Priorities ................................................................................................ 65
12.1.2.Interrupt Latency.................................................................................................. 65
12.2.Interrupt Control Registers........................................................................................... 67
13. Power Management and Internal Regulator .................................................................... 74
13.1.Power Modes ...............................................................................................................74
13.1.1.Idle Mode............................................................................................................. 74
13.1.2.Stop Mode ........................................................................................................... 75
13.2.LDO Regulator .............................................................................................................75
13.3.Power Control Registers .............................................................................................. 75
13.4.LDO Control Registers.................................................................................................76
14. Analog-to-Digital Converter (ADC0)................................................................................. 78
14.1.ADC0 Analog Multiplexer............................................................................................. 79
14.2.ADC Operation.............................................................................................................80
14.2.1.Starting a Conversion ..........................................................................................80
14.2.2.Tracking Modes ................................................................................................... 80
14.2.3.Burst Mode .......................................................................................................... 81
14.2.4.Settling Time Requirements ................................................................................ 82
14.2.5.Gain Setting......................................................................................................... 83
14.3.8-Bit Mode.................................................................................................................... 83
14.4.12-Bit Mode.................................................................................................................. 83
14.5.Power Considerations.................................................................................................. 84
14.6.Output Code Formatting .............................................................................................. 86
14.7.Programmable Window Detector ................................................................................. 87
14.7.1.Window Detector In Single-Ended Mode............................................................. 87
14.8.Voltage and Ground Reference Options...................................................................... 89
14.8.1.External Voltage Reference................................................................................. 89
14.8.2.Internal Voltage Reference.................................................................................. 89
14.8.3.Analog Ground Reference...................................................................................89
Preliminary Rev 0.6
3
C8051F85x/86x
14.9.Temperature Sensor .................................................................................................... 90
14.9.1.Calibration ........................................................................................................... 90
14.10.ADC Control Registers............................................................................................... 91
15. CIP-51 Microcontroller Core ........................................................................................... 106
15.1.Performance .............................................................................................................. 106
15.2.Programming and Debugging Support ...................................................................... 107
15.3.Instruction Set ............................................................................................................ 107
15.3.1.Instruction and CPU Timing............................................................................... 107
15.4.CPU Core Registers .................................................................................................. 112
16. Clock Sources and Selection (HFOSC0, LFOSC0, and EXTCLK)................................ 118
16.1.Programmable High-Frequency Oscillator................................................................. 118
16.2.Programmable Low-Frequency Oscillator.................................................................. 118
16.2.1.Calibrating the Internal L-F Oscillator ................................................................ 118
16.3.External Clock............................................................................................................118
16.4.Clock Selection .......................................................................................................... 119
16.5.High Frequency Oscillator Control Registers............................................................. 120
16.6.Low Frequency Oscillator Control Registers.............................................................. 121
16.7.Clock Selection Control Registers ............................................................................. 122
17. Comparators (CMP0 and CMP1)..................................................................................... 123
17.1.System Connectivity .................................................................................................. 123
17.2.Functional Description ...............................................................................................126
17.3.Comparator Control Registers ................................................................................... 127
18. Cyclic Redundancy Check Unit (CRC0)......................................................................... 133
18.1.CRC Algorithm ........................................................................................................... 133
18.2.Preparing for a CRC Calculation................................................................................ 135
18.3.Performing a CRC Calculation................................................................................... 135
18.4.Accessing the CRC0 Result....................................................................................... 135
18.5.CRC0 Bit Reverse Feature ........................................................................................135
18.6.CRC Control Registers .............................................................................................. 136
19. External Interrupts (INT0 and INT1)................................................................................ 142
19.1.External Interrupt Control Registers........................................................................... 143
20. Programmable Counter Array (PCA0)............................................................................ 146
20.1.PCA Counter/Timer.................................................................................................... 147
20.2.PCA0 Interrupt Sources ............................................................................................. 147
20.3.Capture/Compare Modules........................................................................................148
20.3.1.Output Polarity................................................................................................... 148
20.3.2.Edge-triggered Capture Mode ........................................................................... 149
20.3.3.Software Timer (Compare) Mode ...................................................................... 150
20.3.4.High-Speed Output Mode.................................................................................. 151
20.3.5.Frequency Output Mode.................................................................................... 152
20.4.PWM Waveform Generation ...................................................................................... 153
20.4.1.Edge Aligned PWM ........................................................................................... 153
20.4.2.Center Aligned PWM ......................................................................................... 155
20.4.3. 8 to11-bit Pulse Width Modulator Modes.......................................................... 157
20.4.4. 16-Bit Pulse Width Modulator Mode ................................................................. 158
20.5.Comparator Clear Function........................................................................................159
4
Preliminary Rev 0.6
C8051F85x/86x
20.6.PCA Control Registers...............................................................................................160
21. Port I/O (Port 0, Port 1, Port 2, Crossbar, and Port Match) .......................................... 178
21.1.General Port I/O Initialization ..................................................................................... 179
21.2.Assigning Port I/O Pins to Analog and Digital Functions ........................................... 180
21.2.1.Assigning Port I/O Pins to Analog Functions.....................................................180
21.2.2.Assigning Port I/O Pins to Digital Functions ...................................................... 180
21.2.3.Assigning Port I/O Pins to Fixed Digital Functions ............................................ 181
21.3.Priority Crossbar Decoder.......................................................................................... 182
21.4.Port I/O Modes of Operation ...................................................................................... 184
21.4.1.Configuring Port Pins For Analog Modes .......................................................... 184
21.4.2.Configuring Port Pins For Digital Modes ........................................................... 184
21.4.3.Port Drive Strength ............................................................................................ 184
21.5.Port Match.................................................................................................................. 185
21.6.Direct Read/Write Access to Port I/O Pins................................................................. 185
21.7.Port I/O and Pin Configuration Control Registers ...................................................... 186
22. Reset Sources and Supply Monitor ............................................................................... 204
22.1.Power-On Reset ........................................................................................................ 205
22.2.Power-Fail Reset / Supply Monitor ............................................................................ 206
22.3.Enabling the VDD Monitor ......................................................................................... 206
22.4.External Reset ........................................................................................................... 207
22.5.Missing Clock Detector Reset.................................................................................... 207
22.6.Comparator0 Reset.................................................................................................... 207
22.7.Watchdog Timer Reset .............................................................................................. 207
22.8.Flash Error Reset....................................................................................................... 207
22.9.Software Reset .......................................................................................................... 207
22.10.Reset Sources Control Registers............................................................................. 208
23. Serial Peripheral Interface (SPI0) ................................................................................... 214
23.1.Signal Descriptions .................................................................................................... 215
23.1.1.Master Out, Slave In (MOSI) ............................................................................. 215
23.1.2.Master In, Slave Out (MISO) ............................................................................. 215
23.1.3.Serial Clock (SCK)............................................................................................. 215
23.1.4.Slave Select (NSS)............................................................................................ 215
23.2.SPI0 Master Mode Operation .................................................................................... 216
23.3.SPI0 Slave Mode Operation ...................................................................................... 218
23.4.SPI0 Interrupt Sources...............................................................................................218
23.5.Serial Clock Phase and Polarity.................................................................................218
23.6.SPI Special Function Registers .................................................................................220
23.7.SPI Control Registers ................................................................................................ 224
24. System Management Bus / I2C (SMBus0) ..................................................................... 229
24.1.Supporting Documents .............................................................................................. 230
24.2.SMBus Configuration ................................................................................................. 230
24.3.SMBus Operation....................................................................................................... 230
24.3.1.Transmitter vs. Receiver.................................................................................... 231
24.3.2.Arbitration .......................................................................................................... 231
24.3.3.Clock Low Extension ......................................................................................... 231
24.3.4.SCL Low Timeout .............................................................................................. 231
Preliminary Rev 0.6
5
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