GD82541GI datasheet, PDF - EEWORLD Datasheet

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GD82541GI: Description1 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196; CategoryThe embedded processor and controller Microcontrollers and processors; File Size437KB，46 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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GD82541GI Overview

1 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196

GD82541GI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
Parts packaging code	BGA
package instruction	BGA, BGA196,14X14,40
Contacts	196
Reach Compliance Code	compli
Address bus width	32
boundary scan	YES
Bus compatibility	PCI
maximum clock frequency	25 MHz
Data encoding/decoding methods	NRZ; NRZI; BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	125 MBps
External data bus width	32
JESD-30 code	S-PBGA-B196
length	15 mm
low power mode	YES
Number of serial I/Os	1
Number of terminals	196
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA196,14X14,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	240
power supply	1.2,1.8,3.3 V
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage	1.26 V
Minimum supply voltage	1.14 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	15 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches	1

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82541 Family of Gigabit Ethernet

Controllers

Networking Silicon - 82541(PI/GI/EI)

Datasheet

Product Features

■

PCI Bus

— PCI revision 2.3, 32-bit, 33/66 MHz

— Algorithms that optimally use advanced PCI,

MWI, MRM, and MRL commands

— CLK_RUN# signal

— 3.3 V (5 V tolerant PCI signaling)

MAC Specific

— Low-latency transmit and receive queues

— IEEE 802.3x-compliant flow-control support

with software-controllable thresholds

— Caches up to 64 packet descriptors in a single

burst

— Programmable host memory receive buffers

(256 B to 16 KB) and cache line size (16 B to

256 B)

— Wide, optimized internal data path

architecture

— 64 KB configurable Transmit and Receive

FIFO buffers

PHY Specific

— Integrated for 10/100/1000 Mb/s full- and

half-duplex operation

— IEEE 802.3ab Auto-Negotiation and PHY

compliance and compatibility

— State-of-the-art DSP architecture implements

digital adaptive equalization, echo and cross-

talk cancellation

— Automatic polarity detection

— Automatic detection of cable lengths and

MDI vs. MDI-X cable at all speeds

■

Host Off-Loading

— Transmit and receive IP, TCP, and UDP

checksum off-loading capabilities

— Transmit TCP segmentation and advanced

packed filtering

— IEEE 802.1Q VLAN tag insertion and

stripping and packet filtering for up to 4096

VLAN tags

— Jumbo frame support up to 16 KB

— Intelligent Interrupt generation (multiple

packets per interrupt)

Manageability

— On-chip SMBus 2.0 port

— ASF 1.0 and 2.0

— Compliance with PCI Power Management

v1.1/ACPI v2.0

— Wake on LAN* (WoL) support

— Smart Power Down mode when no signal is

detected on the wire

— Power Save mode switches link speed from

1000 Mb/s down to 10 or 100 Mb/s when on

battery power

Additional Device

— Four programmable LED outputs

— On-chip power regulator control circuitry

— BIOS LAN Disable pin

— JTAG (IEEE 1149.1) Test Access Port built

in silicon (3.3 V, 5 V tolerant PCI signaling)

Lead-free

196-pin Ball Grid Array (BGA).

Devices that are lead-free are marked with a

circled “e1” and have the product code:

LUxxxxxx.

a. This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at

<1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other

Restriction on Hazardous Substances (RoHS)-banned materials, is available at:

ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks

In addition, this device has been tested and conforms to the same parametric specifications as previous versions of

the device.

For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales represen-

tative

318138-002

Revision 2.7

Networking Silicon — 82541(PI/GI/EI)

Contents

1.0

Introduction......................................................................................................................... 7

1.1

1.2

1.3

2.0

2.1

2.2

2.3

2.4

3.0

3.1

3.2

Document Scope................................................................................................... 7

Reference Documents...........................................................................................8

Product Codes....................................................................................................... 8

External Architecture Block Diagram...................................................................11

Internal MAC Architecture Block Diagram...........................................................12

Integrated 10/100/1000Mbps PHY ......................................................................12

System Interface .................................................................................................12

Signal Type Definitions........................................................................................11

PCI Bus Interface Signals (56) ............................................................................11

3.2.1 PCI Address, Data and Control Signals (44) ..........................................12

3.2.2 Arbitration Signals (2).............................................................................13

3.2.3 Interrupt Signal (1)..................................................................................13

3.2.4 System Signals (4) .................................................................................13

3.2.5 Error Reporting Signals (2).....................................................................14

3.2.6 Power Management Signals (3) .............................................................14

3.2.7 SMB Signals (3) .....................................................................................14

EEPROM and Serial FLASH Interface Signals (9)..............................................15

Miscellaneous Signals.........................................................................................15

3.4.1 LED Signals (4) ......................................................................................15

3.4.2 Other Signals (4) ....................................................................................16

PHY Signals ........................................................................................................16

3.5.1 Crystal Signals (2) ..................................................................................16

3.5.2 Analog Signals (10) ................................................................................16

Test Interface Signals (6) ....................................................................................17

Power Supply Connections .................................................................................17

3.7.1 Digital and Analog Supplies ...................................................................17

3.7.2 Grounds, Reserved Pins and No Connects ...........................................18

3.7.3 Voltage Regulation Control Signals (2) ..................................................18

Absolute Maximum Ratings.................................................................................19

Targeted Recommended Operating Conditions..................................................19

4.2.1 General Operating Conditions................................................................19

4.2.2 Voltage Ramp and Sequencing Recommendations...............................20

DC Specifications ................................................................................................22

AC Characteristics...............................................................................................25

Timing Specifications ..........................................................................................27

Package Information ...........................................................................................33

Thermal Specifications ........................................................................................35

Pinout Information ...............................................................................................36

Architectural Overview .....................................................................................................11

Signal Descriptions...........................................................................................................11

3.3

3.4

3.5

3.6

3.7

4.0

Voltage, Temperature, and Timing Specifications............................................................19

4.1

4.2

4.3

4.4

4.5

5.0

5.1

5.2

5.3

Package and Pinout Information ......................................................................................33

iii

82541(PI/GI/EI) — Networking Silicon

5.4

Visual Pin Assignments....................................................................................... 46

Figures

82541(PI/GI/EI) External Architecture Block Diagram ........................................ 11

Internal Architecture Block Diagram.................................................................... 12

AC Test Loads for General Output Pins.............................................................. 27

AC Test Loads for General Output Pins.............................................................. 28

AC Test Loads for General Output Pins.............................................................. 29

TVAL (max) Rising Edge Test Load.................................................................... 30

TVAL (max) Falling Edge Test Load ................................................................... 30

TVAL (min) Test Load ......................................................................................... 30

TVAL Test Load (PCI 5 V Signaling Environment) ............................................. 31

Link Interface Rise/Fall Timing............................................................................ 31

82541(PI/GI/EI) Mechanical Specifications......................................................... 33

196 PBGA Package Pad Detail........................................................................... 34

Visual Pin Assignments....................................................................................... 46

Tables

Absolute Maximum Ratings ................................................................................ 19

Recommended Operating Conditions ................................................................ 19

3.3V Supply Voltage Ramp ................................................................................. 20

1.8V Supply Voltage Ramp ................................................................................. 20

1.2V Supply Voltage Ramp ................................................................................. 21

DC Characteristics .............................................................................................. 22

Power Specifications - D0a ................................................................................. 22

Power Specifications - D3cold ............................................................................ 23

Power Specifications D(r) Uninitialized ............................................................... 23

Power Specifications - Complete Subsystem ..................................................... 24

I/O Characteristics............................................................................................... 24

AC Characteristics: 3.3 V Interfacing .................................................................. 25

25 MHz Clock Input Requirements ..................................................................... 25

Reference Crystal Specification Requirements................................................... 26

Link Interface Clock Requirements ..................................................................... 26

EEPROM Interface Clock Requirements ............................................................ 26

PCI Bus Interface Clock Parameters .................................................................. 27

PCI Bus Interface Timing Parameters................................................................. 28

PCI Bus Interface Timing Measurement Conditions ........................................... 29

Link Interface Rise and Fall Times...................................................................... 31

EEPROM Link Interface Clock Requirements..................................................... 32

Thermal Characteristics ...................................................................................... 35

PCI Address, Data and Control Signals .............................................................. 36

PCI Arbitration Signals ........................................................................................ 36

Interrupt Signals .................................................................................................. 36

System Signals ................................................................................................... 36

Error Reporting Signals....................................................................................... 37

Power Management Signals ............................................................................... 37

SMB Signals........................................................................................................ 37

GD82541GI Related Products

	GD82541GI	GD82541EI	GD82541PI	LU82541EI	LU82541GI	LU82541PI
Description	1 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196	1 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196	1 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196	1 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196	1 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196	1 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196
Is it Rohs certified?	incompatible	incompatible	incompatible	conform to	conform to	conform to
Maker	Intel	Intel	Intel	Intel	Intel	Intel
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	BGA, BGA196,14X14,40	BGA, BGA196,14X14,40	BGA, BGA196,14X14,40	BGA, BGA196,14X14,40	BGA, BGA196,14X14,40	BGA, BGA196,14X14,40
Contacts	196	196	196	196	196	196
Reach Compliance Code	compli	unknown	compli	compli	compli	compli
Address bus width	32	32	32	32	32	32
boundary scan	YES	YES	YES	YES	YES	YES
Bus compatibility	PCI	PCI	PCI	PCI	PCI	PCI
maximum clock frequency	25 MHz	25 MHz	25 MHz	25 MHz	25 MHz	25 MHz
Data encoding/decoding methods	NRZ; NRZI; BIPH-LEVEL(MANCHESTER)	NRZ; NRZI; BIPH-LEVEL(MANCHESTER)	NRZ; NRZI; BIPH-LEVEL(MANCHESTER)	NRZ; NRZI; BIPH-LEVEL(MANCHESTER)	NRZ; NRZI; BIPH-LEVEL(MANCHESTER)	NRZ; NRZI; BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	125 MBps	125 MBps	125 MBps	125 MBps	125 MBps	125 MBps
External data bus width	32	32	32	32	32	32
JESD-30 code	S-PBGA-B196	S-PBGA-B196	S-PBGA-B196	S-PBGA-B196	S-PBGA-B196	S-PBGA-B196
length	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm
low power mode	YES	YES	YES	YES	YES	YES
Number of serial I/Os	1	1	1	1	1	1
Number of terminals	196	196	196	196	196	196
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA	BGA
Encapsulate equivalent code	BGA196,14X14,40	BGA196,14X14,40	BGA196,14X14,40	BGA196,14X14,40	BGA196,14X14,40	BGA196,14X14,40
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
power supply	1.2,1.8,3.3 V	1.2,1.8,3.3 V	1.2,1.8,3.3 V	1.2,1.8,3.3 V	1.2,1.8,3.3 V	1.2,1.8,3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm
Maximum supply voltage	1.26 V	1.26 V	1.26 V	1.26 V	1.26 V	1.26 V
Minimum supply voltage	1.14 V	1.14 V	1.14 V	1.14 V	1.14 V	1.14 V
Nominal supply voltage	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, LAN	SERIAL IO/COMMUNICATION CONTROLLER, LAN	SERIAL IO/COMMUNICATION CONTROLLER, LAN	SERIAL IO/COMMUNICATION CONTROLLER, LAN	SERIAL IO/COMMUNICATION CONTROLLER, LAN	SERIAL IO/COMMUNICATION CONTROLLER, LAN
Peak Reflow Temperature (Celsius)	240	225	240	-	-	260
Maximum time at peak reflow temperature	30	NOT SPECIFIED	30	-	-	40
Is it lead-free?	-	-	Contains lead	Lead free	Lead free	Lead free
JESD-609 code	-	-	e0	e1	e1	e1
Terminal surface	-	-	TIN LEAD	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER

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