EEWORLDEEWORLDEEWORLD

Part Number

Search

VF961SH-C-FREQ-OUT7

Description
PECL Output Clock Oscillator, 10MHz Min, 200MHz Max, DIP-5
CategoryPassive components    oscillator   
File Size92KB,1 Pages
ManufacturerCTS [CTS Corporation]
Download Datasheet Parametric View All

VF961SH-C-FREQ-OUT7 Overview

PECL Output Clock Oscillator, 10MHz Min, 200MHz Max, DIP-5

VF961SH-C-FREQ-OUT7 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerCTS [CTS Corporation]
Reach Compliance Codeunknown
Maximum control voltage5 V
Minimum control voltage
maximum descent time1.5 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate50 ppm
frequency stability20%
linearity20%
Manufacturer's serial numberVF961
Installation featuresTHROUGH HOLE MOUNT
Maximum operating frequency200 MHz
Minimum operating frequency10 MHz
Maximum operating temperature70 °C
Minimum operating temperature
Oscillator typePECL
Output load50 OHM
physical size20.32mm x 12.62mm x 4.75mm
longest rise time1.5 ns
Nominal supply voltage5 V
surface mountNO
maximum symmetry55/45 %
Where do you buy components?
Everyone buys components in local places. I am a component salesman and I don’t know how to find customers. I would like to ask you masters where do you purchase. I work with imported materials such a...
世通371276312 Analogue and Mixed Signal
Assembly sorting (waiting online...)
代码如下。。。。。。。。DATA SEGMENTXX DB 10, 9, 8, 7, 6, 5, 4, 3, 2,1, 0DH, 0AH, '$'IDB 9JDB 0LASTXCHGDB ?STACK SEGMENTDB 100 DUP(?)STACK ENDSDATA ENDSCODE SEGMENTASSUME CS:CODE,DS:DATA,SS:STACKSTART:MOV AX,DATA...
liuwy Embedded System
How does 6045 generate pwm waves
How to use pwm wave to adjust the backlight on the 6045 development board launched by Shenzhen Tianmo Technology Company? I made corresponding modifications to the board-sam9m10g45ek.c file in the ker...
yjh19891026 Linux and Android
Solution for buffer simulation not working
This statement SYSCLK: buffer std_logic; will report an error during simulation, so you need to change this statement SYSCLK: OUT STD_LOGIC;. At this time, sysclk is defined as the OUT output signal. ...
刘123 FPGA/CPLD
DSP5509 Schematic Diagram
DSP5509 schematic diagram...
Jacktang DSP and ARM Processors
Sharing of self-built Altium Designer 3D library
Self-built AD9 3D practice model file:Built PCB library with 3D:CAD plan:[[i] This post was last edited by Qingye Piaoling on 2013-12-4 18:01[/i]]...
青叶漂零 PCB Design

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 852  2370  187  801  2014  18  48  4  17  41 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号