K4S641633F-R(B)L/N/P
1M x 16Bit x 4 Banks SDRAM in 54CSP
FEATURES
• 3.0V & 3.3V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1 & 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
• Commercial Temperature Operation (-25°C ~ 70
°C).
Extended Temperature Operation (-25°C ~ 85°C).
Industrial Temperature Operation (-40°C ~ 85°C).
• 54balls CSP (-RXXX - Pb, -BXXX - Pb Free)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S641633F is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 1,048,576 words by 16
bits, fabricated with SAMSUNG’s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock and I/O transactions are possible
on every clock cycle. Range of operating frequencies, program-
mable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
ORDERING INFORMATION
Part No.
K4S641633F-R(B)L/N/P75
K4S641633F-R(B)L/N/P1H
Max Freq.
133MHz(CL3)
105MHz(CL2)
105MHz(CL2)
LVCMOS
Interface Package
54 CSP
Pb
(Pb Free)
K4S641633F-R(B)L/N/P1L 105MHz(CL3)
*1
-R(B)L : Low Power, Operating Temp : -25°C ~ 70
°C.
-R(B)N : Low Power, Operating Temp : -25°C ~ 85
°C.
-R(B)P : Low Power, Operating Temp : -40
°C
~ 85°C.
Note :
1. In case of 40MHz Frequency, CL1 can be supported.
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
LDQM
Data Input Register
Bank Select
1M x 16
1M x 16
1M x 16
1M x 16
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.4 Dec. 2002
K4S641633F-R(B)L/N/P
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
I N
, V
OUT
V
DD
, V
DDQ
T
S T G
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
CMOS SDRAM
Unit
V
V
°C
W
mA
Note
:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to V
SS
= 0V, T
A
=Commercial, Extended, Industrial Temperature)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
D D
V
DDQ
V
I H
V
IL
V
O H
V
OL
I
LI
Min
2.7
2.7
2.2
-0.3
2.4
-
-10
Typ
3.0
3.0
3.0
0
-
-
-
Max
3.6
3.6
V
DDQ
+0.3
0.5
-
0.4
10
Unit
V
V
V
V
V
V
uA
1
2
I
O H
= -2mA
I
OL
= 2mA
3
Note
Note
:
1. V
IH
(max) = 5.3V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DDQ.
CAPACITANCE
(V
DD
= 3.0V or 3.3V, T
A
= 23°C, f = 1MHz, V
REF
=0.9V
±
50 mV)
Pin
Clock
RAS, CAS, WE, CS, CKE, DQM
Address
DQ
0
~ DQ
15
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
2.0
2.0
2.0
3.5
Max
4.0
4.0
4.0
6.0
Unit
pF
pF
pF
pF
Note
Rev. 1.4 Dec. 2002
K4S641633F-R(B)L/N/P
DC CHARACTERISTICS
CMOS SDRAM
Recommended operating conditions(Voltage referenced to V
SS
= 0V, T
A
=Commercial, Extended, Industrial Temperature)
Parameter
Symbol
Burst length = 1
t
RC
≥
t
R C
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
Test Condition
-75
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
I
CC1
60
Version
-1H
55
-1L
55
mA
1
Unit
Note
I
CC2
P
0.5
0.5
11
I
C C 2
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
= 10ns
mA
Precharge Standby Current
in non power-down mode
I
CC2
NS
Active Standby Current
in power-down mode
I
CC3
P
mA
8
5
5
22
mA
I
C C 3
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
C C D
= 2CLKs
t
RC
≥
t
R C
(min)
-R(B)L
CKE
≤
0.2V
mA
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
NS
22
mA
Operating Current
(Burst Mode)
I
CC4
90
70
70
mA
1
Refresh Current
I
CC5
135
120
120
mA
2
3
Self Refresh Current
I
CC6
-R(B)N
-R(B)P
400
uA
4
5
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S641633F-R(B)L**
4. K4S641633F-R(B)N**
5. K4S641633F-R(B)P**
6. Unless otherwise noted, input swing IeveI is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ)
Rev. 1.4 Dec. 2002
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