The X28C512, X28C513 are 64K x 8 EEPROM, fabricated
with Intersil’s proprietary, high performance, floating gate
CMOS technology. Like all Intersil programmable nonvolatile
memories, the X28C512, X28C513 are 5V only devices. The
X28C512, X28C513 feature the JEDEC approved pin out for
byte wide memories, compatible with industry standard
EPROMS.
The X28C512, X28C513 support a 128-byte page write
operation, effectively providing a 39µs/byte write cycle and
enabling the entire memory to be written in less than 2.5
seconds. The X28C512, X28C513 also feature DATA Polling
and Toggle Bit Polling, system software support schemes
used to indicate the early completion of a write cycle. In
addition, the X28C512, X28C513 support the software data
protection option.
Features
• Access Time: 90ns
• Simple Byte and Page Write
- Single 5V supply
• No external high voltages or V
PP
control circuits
- Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
• Low Power CMOS
- Active: 50mA
- Standby: 500µA
• Software Data Protection
- Protects data against system level inadvertent writes
• High Speed Page Write Capability
• Highly Reliable Direct Write
™
Cell
- Endurance: 100,000 write cycles
- Data retention: 100 years
- Early end of write detection
- DATA polling
- Toggle bit polling
• Two PLCC and LCC Pinouts
- X28C512
• X28C010 EPROM pin compatible
- X28C513
• Compatible with lower density EEPROMs
• Pb-Free Plus Anneal Available (RoHS Compliant)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X28C512, X28C513
Block Diagram
A
7
-A
15
X Buffers
Latches and
Decoder
512Kbit
EEPROM
Array
A
0
-A
6
Y Buffers
Latches and
Decoder
I/O Buffers
and Latches
I/O
0
-I/O
7
CE
OE
WE
V
CC
V
SS
Control
Logic and
Timing
Data Inputs/Outputs
Ordering Information
PART NUMBER
X28C512D
X28C512DM
X28C512J
X28C513EM
X28C512D-12
X28C512DI-12
X28C512DMB-12
X28C512FMB-12
X28C512J-12*
X28C512JZ-12* (See Note)
X28C512JI-12
X28C512JIZ-12* (See Note)
X28C512JM-12
X28C512KM-12
X28C512PI-12
X28C512RMB-12
X28C513EM-12
X28C513EMB-12
X28C513J-12*
X28C513JZ-12* (Note)
X28C513JI-12*
X28C513JIZ-12* (Note)
X28C513JM-12
PART MARKING
X28C512D
X28C512DM
X28C512J
X28C513EM
X28C512D-12
X28C512DI-12
X28C512DMB-12
X28C512FMB-12
X28C512J-12
X28C512J-12 Z
X28C512JI-12
X28C512JI-12 Z
X28C512JM-12
X28C512KM-12
X28C512PI-12
X28C512RMB-12
X28C513EM-12
X28C513EMB-12
X28C513J-12
X28C513J-12 Z
X28C513JI-12
X28C513JI-12 Z
X28C513JM-12
120
ACCESS TIME
(ns)
-
TEMP RANGE (°C)
0 to +70
-55 to +125
0 to +70
-55 to +125
0 to +70
-40 to +85
Mil-STD-883
Mil-STD-883
0 to +70
0 to +70
-40 to +85
-40 to +85
-55 to +125
-55 to +125
-40 to +85
Mil-STD-883
-55 to +125
Mil-STD-883
0 to +70
0 to +70
-40 to +85
-40 to +85
-55 to +125
PACKAGE
32 Ld CERDIP
32 Ld CERDIP
32 Ld PLCC
32 Ld LCC
32 Ld CERDIP
32 Ld CERDIP
32 Ld CERDIP
32 Ld Flat Pack
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
36 Ld CPGA
32 Ld PDIP
32 Ld Flat Pack
32 Ld LCC
32 Ld LCC
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
2
FN8106.2
June 7, 2006
X28C512, X28C513
Ordering Information
(Continued)
PART NUMBER
X28C512D-15
X28C512DI-15
X28C512DMB-15
X28C512J-15*
X28C512JZ-15* (See Note)
X28C512JI-15*
X28C512JIZ-15* (See Note)
X28C512JM-15
X28C513EM-15
X28C513EMB-15
X28C513J-15*
X28C513JZ-15* (Note)
X28C513JI-15
X28C513JIZ-15* (Note)
X28C513JM-15
X28C512DMB-20
X28C512JM-20
X28C512KI-20
X28C512KM-20
X28C513EI-20
X28C513EM-20
X28C513EMB-20
X28C513J-20T1
X28C512EM-25
X28C512JM-25
X28C512KM-25
X28C512KMB-25
X28C513EM-25
X28C513EMB-25
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PART MARKING
X28C512D-15
X28C512DI-15
X28C512DMB-15
X28C512J-15
X28C512J-15 Z
X28C512JI-15
X28C512JI-15 Z
X28C512JM-15
X28C513EM-15
X28C513EMB-15
X28C513J-15
X28C513J-15 Z
X28C513JI-15
X28C513JI-15 Z
X28C513JM-15
X28C512DMB-20
X28C512JM-20
X28C512KI-20
X28C512KM-20
X28C513EI-20
X28C513EM-20
X28C513EMB-20
X28C513J-20
X28C512EM-25
X28C512JM-25
X28C512KM-25
X28C512KMB-25
X28C513EM-25
X28C513EMB-25
ACCESS TIME
(ns)
150
TEMP RANGE (°C)
0 to +70
-40 to +85
Mil-STD-883
0 to +70
0 to +70
-40 to +85
-40 to +85
-55 to +125
-55 to +125
Mil-STD-883
0 to +70
0 to +70
-40 to +85
-40 to +85
-55 to +125
PACKAGE
32 Ld CERDIP
32 Ld CERDIP
32 Ld CERDIP
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
32 Ld LCC
32 Ld LCC
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
32 Ld CERDIP
32 Ld PLCC
36 Ld CPGA
36 Ld CPGA
32 Ld LCC
32 Ld LCC
32 Ld LCC
32 Ld PLCC Tape and Reel
32 Ld LCC
32 Ld PLCC
36 Ld CPGA
36 Ld CPGA
32 Ld LCC
32 Ld LCC
200
Mil-STD-883
-55 to +125
-40 to +85
-55 to +125
-40 to +85
-55 to +125
Mil-STD-883
0 to +70
250
-55 to +125
-55 to +125
-55 to +125
Mil-STD-883
-55 to +125
Mil-STD-883
3
FN8106.2
June 7, 2006
X28C512, X28C513
Pinouts
PLCC/LCC
A
15
NC
NC
V
CC
WE
A
12
Plastic DIP
CERDIP
FLAT Pack
SOIC (R)
NC
NC
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE
NC
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
6
A
1
13
A
2
12
A
4
10
A
6
8
A
12
I/O
0
15
A
0
14
A
3
11
9
A
5
A
7
7
A
15
5
NC
4
3
NC
2
NC
I/O
2
17
A
7
54 3 2
6
7
8
9
10
11
PGA
I/O
5
I/O
3
21
19
I/O
6
22
CE
24
OE
26
A
9
28
A
13
30
A
14
31
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
30
32 31 29
1
28
27
26
25
24
23
NC
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
27
26
25
24
23
A
8
A
9
A
11
NC
OE
A
10
I/O
5
X28C512
(Top View)
I/O
4
I/O
1
V
SS
I/O
7
20
16
18
23
A
10
25
12
22
13 15 16 17 18 19 20
21
14
I/O
1
I/O
2
V
SS
A
12
A
14
A
7
I/O
3
I/O
4
I/O
5
NC
I/O
3
I/O
4
Bottom
View
V
CC
36
NC
1
NC
34
WE
35
A
11
27
A
8
29
NC
32
NC
33
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
54 3 2
6
7
8
9
10
11
X28C513
(Top View)
CE
I/O
7
12
22
13 15 16 17 18 19 20
I/O
6
21
14
I/O
1
I/O
2
V
SS
Pin Descriptions
Addresses (A
0
-A
15
)
The Address inputs select an 8-bit memory location during a
read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is
reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers and
is used to initiate read operations.
Data In/Data Out (I/O
0
-I/O
7
)
Data is written to or read from the X28C512, X28C513
through the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
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