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A54SX32A-3PQ208A

Description
Field Programmable Gate Array, 2880 CLBs, 48000 Gates, CMOS, PQFP208, PLASTIC, QFP-208
CategoryProgrammable logic devices    Programmable logic   
File Size2MB,83 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

A54SX32A-3PQ208A Overview

Field Programmable Gate Array, 2880 CLBs, 48000 Gates, CMOS, PQFP208, PLASTIC, QFP-208

A54SX32A-3PQ208A Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Objectid1822045980
package instructionPLASTIC, QFP-208
Reach Compliance Codeunknown
Other features32000 TYPICAL GATES AVAILABLE
Combined latency of CLB-Max0.8 ns
JESD-30 codeS-PQFP-G208
JESD-609 codee0
length28 mm
Humidity sensitivity level3
Configurable number of logic blocks2880
Equivalent number of gates48000
Number of terminals208
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
organize2880 CLBS, 48000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeFQFP
Package shapeSQUARE
Package formFLATPACK, FINE PITCH
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height4.1 mm
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
width28 mm
v4.0
SX-A Family FPGAs
Le a di n g- E d ge P er f o r m a n ce
u e
• 250 MHz System Performance
• 350 MHz Internal Performance
• 3.8 ns Clock-to-Out (Pad-to-Pad)
S p e ci f i c a t i on s
12,000 to 108,000 Available System Gates
Up to 360 User-Programmable I/O Pins
Up to 2,012 Dedicated Flip-Flops
0.22
µ
/0.25
µ
CMOS Process Technology
• Configurable I/O Support for 3.3V/5V PCI, 5V TTL,
3.3V LVTTL, 2.5V LVCMOS2
• 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input
Tolerance and 5V Drive Strength
• Devices Support Multiple Temperature Grades
• Configurable Weak-Resistor Pull-up or Pull-down for
Outputs at Power-up
• Individual Output Slew Rate Control
• Up to 100% Resource Utilization and 100% Pin Locking
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
• Actel’s Secure Programming Technology with FuseLock™
Prevents Reverse Engineering and Design Theft
Fe a t ur es
• Hot-Swap Compliant I/Os
• Power-up/down Friendly (No Sequencing Required for
Supply Voltages)
• 66 MHz PCI Compliant
• Single-Chip Solution
• Nonvolatile
SX - A P r od u ct P r o f i l e
Device
A54SX08A
A54SX16A
A54SX32A
A54SX72A
Capacity
Typical Gates
8,000
16,000
32,000
72,000
System Gates
12,000
24,000
48,000
108,000
Logic Modules
768
1,452
2,880
6,036
Combinatorial Cells
512
924
1,800
4,024
Register Cells
Dedicated Flip-Flops
256
528
1,080
2,012
Maximum Flip-Flops
512
990
1,980
4,024
Maximum User I/Os
130
180
249
360
3
3
3
3
Global Clocks
Quadrant Clocks
0
0
0
4
Boundary Scan Testing
Yes
Yes
Yes
Yes
3.3V/5V PCI
Yes
Yes
Yes
Yes
Clock-to-Out
4.2 ns
4.6 ns
4.7 ns
5.8 ns
Input Set-Up (External)
0 ns
0 ns
0 ns
0 ns
Speed Grades
–F, Std, –1, –2, –3 –F, Std, –1, –2, –3 –F, Std, –1, –2, –3 –F, Std, –1, –2, –3
Temperature Grades
C, I, A
C, I, M, A
C, I, M, A
C, I, M, A
Package
(by pin count)
208
208
208
PQFP
208
100, 144
100, 144, 176
TQFP
100, 144
329
PBGA
256, 484
144, 256
144, 256, 484
FBGA
144
208, 256
208, 256
CQFP*
Note:
For more information about the CQFP package options, refer to the
HiRel SX-A
datasheet at:
www.actel.com/documents/HRSXADS.pdf
A p r i l 20 0 3
1
© 2001 Actel Corporation

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Index Files: 21  1010  80  581  1266  1  21  2  12  26 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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