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V62C3162048L-70TI

Description
Standard SRAM, 128KX16, 70ns, CMOS, PDSO44, TSOP2-44
Categorystorage    storage   
File Size101KB,13 Pages
ManufacturerMosel Vitelic Corporation ( MVC )
Websitehttp://www.moselvitelic.com
Download Datasheet Parametric View All

V62C3162048L-70TI Overview

Standard SRAM, 128KX16, 70ns, CMOS, PDSO44, TSOP2-44

V62C3162048L-70TI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMosel Vitelic Corporation ( MVC )
Objectid1906380246
Parts packaging codeTSOP2
package instructionTSOP2, TSOP44,.46,32
Contacts44
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
compound_id9711027
Maximum access time70 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-G44
JESD-609 codee0
length18.41 mm
memory density2097152 bit
Memory IC TypeSTANDARD SRAM
memory width16
Number of functions1
Number of terminals44
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize128KX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP44,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum standby current0.00001 A
Minimum standby current2.7 V
Maximum slew rate0.045 mA
Maximum supply voltage (Vsup)3.3 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
V62C3162048L(L)
Ultra Low Power
128K x 16 CMOS SRAM
Features
• Low-power consumption
- Active: 65mA I
CC
at 35ns
- Stand-by: 10
µ
A (CMOS input/output)
2
µA
(CMOS input/output, L version)
• 35/45/55/70/85/100 ns access time
• Equal access and cycle time
• Single +2.7V to3.3V Power Supply
• Tri-state output
• Automatic power-down when deselected
• Multiple center power and ground pins for
improved noise immunity
• Individual byte controls for both Read and
Write cycles
• Available in 44 pin TSOP II / 48-fpBGA
Functional Description
The V62C3162048L is a Low Power CMOS Static
RAM organized as 131,072 words by 16 bits. Easy
memory expansion is provided by an active LOW (CE)
and (OE) pin.
This device has an automatic power-down mode feature
when deselected. Separate Byte Enable controls (BLE
and BHE) allow individual bytes to be accessed. BLE
controls the lower bits I/O1 - I/O8. BHE controls the
upper bits I/O9 - I/O16.
Writing to these devices is performed by taking Chip
Enable (CE) with Write Enable (WE) and Byte Enable
(BLE/BHE) LOW.
Reading from the device is performed by taking Chip
Enable (CE) with Output Enable (OE) and Byte Enable
(BLE/BHE) LOW while Write Enable (WE) is held
HIGH.
Logic Block Diagram
Pre-Charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Data
Cont
Data
Cont
Vcc
Vss
TSOPII / 48-fpBGA
Memory Array
1024 X 2048
I/O1 - I/O8
I/O9 - I/O16
I/O Circuit
Column Select
A10 A11 A12 A13 A14 A15 A16
WE
OE
BHE
BLE
CE
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
Row Select
1
REV. 1.2
May
2001 V62C3162048L(L)
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