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HN58C66T-25

Description
EEPROM, 8KX8, 250ns, Parallel, CMOS, PDSO32, PLASTIC, TSOP-32
Categorystorage    storage   
File Size119KB,18 Pages
ManufacturerHitachi (Renesas )
Websitehttp://www.renesas.com/eng/
Download Datasheet Parametric View All

HN58C66T-25 Overview

EEPROM, 8KX8, 250ns, Parallel, CMOS, PDSO32, PLASTIC, TSOP-32

HN58C66T-25 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerHitachi (Renesas )
Parts packaging codeTSOP
package instructionTSOP1, TSSOP32,.56,20
Contacts32
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum access time250 ns
Other features100000 ERASE/WRITE CYCLES; 10 YEARS DATA RETENTION; 32 BYTE PAGE WRITE; AUTOMATIC WRITE
command user interfaceNO
Data pollingYES
Data retention time - minimum10
JESD-30 codeR-PDSO-G32
JESD-609 codee0
length12.4 mm
memory density65536 bit
Memory IC TypeEEPROM
memory width8
Number of functions1
Number of terminals32
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize8KX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP1
Encapsulate equivalent codeTSSOP32,.56,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
page size32 words
Parallel/SerialPARALLEL
power supply5 V
Programming voltage5 V
Certification statusNot Qualified
ready/busyYES
Maximum seat height1.2 mm
Maximum standby current0.001 A
Maximum slew rate0.025 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
switch bitNO
width8 mm
HN58C66 Series
8192-word
×
8-bit CMOS Electrically Erasable and Programmable
CMOS ROM
ADE-203-375F (Z)
Rev. 6.0
Apr. 12, 1995
Description
The Hitachi HN58C66 is a electrically erasable and programmable ROM organized as 8192-word
×
8-bit. It
realizes high speed, low power consumption, and a high level of reliability, employing advanced MNOS
memory technology and CMOS process and circuitry technology. It also has a 32-byte page programming
function to make its erase and write operations faster.
Features
Single 5 V supply
On chip latches: address, data,
CE, OE, WE
Automatic byte write: 10 ms max
Automatic page write (32 bytes): 10 ms max
High speed: Access time 250 ns max
Low power dissipation:
20 mW/MHz typ (active)
2.0 mW typ (standby)
Data
polling, RDY/Busy
Data protection circuit on power on/off
Conforms to JEDEC byte-wide standard
Reliable CMOS with MNOS cell technology
10
5
erase/write cycles (in page mode)
10 years data retension
Write protection by
RES
pin

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