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Intel 850 Chipset: 82850 Memory
Controller Hub (MCH)
Datasheet
®
November 2000
Document Number:
290691-001
82850 MCH
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
850 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
2
2
I C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I C bus/protocol and was developed by Intel. Implementations
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of the I C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM
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*Third-party brands and names are the property of their respective owners.
Copyright © Intel Corporation 2000
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Datasheet
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Contents
1.
Introduction ................................................................................................................................ 11
1.1.
1.2.
1.3.
1.4.
2.
Related Documents....................................................................................................... 11
Terminology................................................................................................................... 11
®
Intel 850 Chipset System ............................................................................................. 13
82850 MCH Overview ................................................................................................... 15
Signal Description ...................................................................................................................... 19
2.1.
2.2.
2.3.
2.4.
2.5.
Host Interface Signals ................................................................................................... 20
Direct RDRAM Interface A ............................................................................................ 22
Direct RDRAM Interface B ............................................................................................ 23
Hub Interface Signals .................................................................................................... 23
AGP Interface Signals ................................................................................................... 24
2.5.1.
AGP Addressing Signals ............................................................................. 24
2.5.2.
AGP Flow Control Signals ........................................................................... 25
2.5.3.
AGP Status Signals..................................................................................... 25
2.5.4.
AGP Strobes ............................................................................................... 26
2.5.5.
AGP/PCI Signals-Semantics ....................................................................... 27
Clocks, Reset, and Miscellaneous ................................................................................ 29
Voltage References, PLL Power ................................................................................... 30
Pin States During Reset ................................................................................................ 31
2.6.
2.7.
2.8.
3.
Register Description................................................................................................................... 33
3.1.
3.2.
3.3.
Register Nomenclature, Definitions, and Access Attributes .......................................... 33
PCI Configuration Space Access .................................................................................. 34
I/O Mapped Registers ................................................................................................... 36
3.3.1.
CONF_ADDR—Configuration Address Register ........................................ 36
3.3.2.
CONF_DATA—Configuration Data Register .............................................. 37
Host-Hub Interface Bridge Device Registers (Device 0) .............................................. 38
3.4.1.
VID—Vendor Identification Register (Device 0) .......................................... 40
3.4.2.
DID—Device Identification Register (Device 0)........................................... 40
3.4.3.
PCICMD—PCI Command Register (Device 0) ........................................... 41
3.4.4.
PCISTS—PCI Status Register (Device 0)................................................... 42
3.4.5.
RID—Revision Identification Register (Device 0)........................................ 43
3.4.6.
SUBC—Sub-Class Code Register (Device 0)............................................. 43
3.4.7.
BCC—Base Class Code Register (Device 0) ............................................. 43
3.4.8.
MLT—Master Latency Timer Register (Device 0)....................................... 44
3.4.9.
HDR—Header Type Register (Device 0) .................................................... 44
3.4.10.
APBASE—Aperture Base Configuration Register (Device 0) ..................... 44
3.4.11.
SVID—Subsystem Vendor ID (Device 0) .................................................... 45
3.4.12.
SID—Subsystem ID (Device 0) ................................................................... 46
3.4.13.
CAPPTR—Capabilities Pointer (Device 0).................................................. 46
3.4.14.
GAR[0:15]—RDRAM Group Architecture Register (Device 0).................... 47
3.4.15.
MCHCFG—MCH Configuration Register (Device 0) .................................. 47
3.4.16.
FDHC—Fixed DRAM Hole Control Register (Device 0) ............................. 49
3.4.17.
PAM[0:6]—Programmable Attribute Map Registers (Device 0) .................. 49
3.4.18.
GBA[0:15]—RDRAM Group Boundary Address Register (Device 0)......... 52
3.4.19.
RDPS—RDRAM Pool Sizing Register (Device 0) ....................................... 53
3.4.
Datasheet
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3.4.20.
3.4.21.
3.4.22.
3.4.23.
3.5.
DRD—RDRAM Device Register Data Register (Device 0) .........................54
RICM—RDRAM Initialization Control Management Register (Device 0).....54
SMRAM—System Management RAM Control Register (Device 0) ...........56
ESMRAMC—Extended System Management RAM Control Register
(Device 0).......................................................................................................57
3.4.24.
ACAPID—AGP Capability Identifier Register (Device 0) .............................58
3.4.25.
AGPSTAT—AGP Status Register (Device 0)..............................................59
3.4.26.
AGPCMD—AGP Command Register (Device 0) ........................................60
3.4.27.
AGPCTRL—AGP Control Register..............................................................61
3.4.28.
APSIZE—Aperture Size (Device 0) .............................................................62
3.4.29.
ATTBASE—Aperture Translation Table Base Regist nennr (Device 0) .....63
3.4.30.
AMTT—AGP Interface Multi-Transaction Timer Register (Device 0).........64
3.4.31.
LPTT—Low Priority Transaction Timer Register (Device 0)........................65
3.4.32.
RDTR—RDRAM Timing Register (Device 0) ..............................................66
3.4.33.
TOM—Top of Low Memory Register (Device 0)..........................................67
3.4.34.
ERRSTS—Error Status Register (Device 0)................................................67
3.4.35.
ERRCMD—Error Command Register (Device 0)........................................69
3.4.36.
SMICMD—SMI Command Register (Device 0)...........................................70
3.4.37.
SCICMD—SCI Command Register (Device 0) ...........................................71
3.4.38.
DRAMRC—RDRAM Refresh Control Register (Device 0) ..........................72
3.4.39.
SKPD—Scratchpad Data (Device 0) ...........................................................72
3.4.40.
DERRCTL_STS—DRAM Error Control/Status Register (Device 0) ...........73
3.4.41.
EAP—Error Address Pointer Register (Device 0)........................................73
3.4.42.
MISC_CNTL—Miscellaneous Control Register (Device 0)..........................74
AGP Bridge Registers (Device 1) ..................................................................................75
3.5.1.
VID1—Vendor Identification Register (Device 1).........................................76
3.5.2.
DID1—Device Identification Register (Device 1) .........................................76
3.5.3.
PCICMD1—PCI-PCI Command Register (Device 1) ..................................77
3.5.4.
PCISTS1—PCI-PCI Status Register (Device 1) ..........................................78
3.5.5.
RID1—Revision Identification Register (Device 1) ......................................78
3.5.6.
SUBC1—Sub-Class Code Register (Device 1) ...........................................79
3.5.7.
BCC1—Base Class Code Register (Device 1) ............................................79
3.5.8.
MLT1—Master Latency Timer Register (Device 1) .....................................79
3.5.9.
HDR1—Header Type Register (Device 1) ...................................................80
3.5.10.
PBUSN1—Primary Bus Number Register (Device 1)..................................80
3.5.11.
SBUSN1—Secondary Bus Number Register (Device 1).............................80
3.5.12.
SUBUSN1—Subordinate Bus Number Register (Device 1) ........................81
3.5.13.
SMLT1—Secondary Master Latency Timer Register (Device 1).................81
3.5.14.
IOBASE1—I/O Base Address Register (Device 1)......................................82
3.5.15.
IOLIMIT1—I/O Limit Address Register (Device 1).......................................82
3.5.16.
SSTS1—Secondary PCI-PCI Status Register (Device 1) ...........................83
3.5.17.
MBASE1—Memory Base Address Register (Device 1) ..............................84
3.5.18.
MLIMIT1—Memory Limit Address Register (Device 1) ...............................84
3.5.19.
PMBASE1—Prefetchable Memory Base Address Register (Device 1).......85
3.5.20.
PMLIMIT1—Prefetchable Memory Limit Address Register (Device 1)........85
3.5.21.
BCTRL1—PCI-PCI Bridge Control Register (Device 1) ..............................86
3.5.22.
ERRCMD1—Error Command Register (Device 1)......................................87
Memory Address Ranges ..............................................................................................89
4.1.1.
VGA and MDA Memory Space ....................................................................90
4.1.2.
PAM Memory Spaces ..................................................................................91
4.1.3.
ISA Hole Memory Space..............................................................................91
4.1.4.
TSEG SMM Memory Space ........................................................................93
4.1.5.
OAPIC Memory Space.................................................................................93
Datasheet
4.
System Address Map .................................................................................................................89
4.1.
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4.2.
4.3.
4.4.
4.5.
System Bus Interrupt APIC Memory Space ................................................ 93
4.1.6.
4.1.7.
High SMM Memory Space .......................................................................... 93
4.1.8.
AGP Aperture Space (Device 0 BAR) ......................................................... 94
4.1.9.
AGP Memory and Prefetchable Memory..................................................... 94
4.1.10.
Hub Interface Subtractive Decode .............................................................. 94
AGP Memory Address Ranges ..................................................................................... 94
4.2.1.
AGP DRAM Graphics Aperture ................................................................... 95
System Management Mode (SMM) Memory Range ..................................................... 95
4.3.1.
SMM Space Definition................................................................................. 96
4.3.2.
SMM Space Restrictions ............................................................................. 96
I/O Address Space ........................................................................................................ 97
MCH Decode Rules and Cross-Bridge Address Mapping............................................. 97
4.5.1.
Hub Interface Decode Rules ....................................................................... 97
4.5.2.
AGP Interface Decode Rules ...................................................................... 98
RDRAM Organization and Configuration..................................................................... 101
5.1.1.
Rules for Populating RDRAM Devices ...................................................... 101
5.1.2.
RDRAM CMOS Signals............................................................................. 102
5.1.3.
Direct RDRAM Core Refresh .................................................................... 103
Direct RDRAM Command Encoding ........................................................................... 104
5.2.1.
Row Packet (ROWA/ROWR).................................................................... 104
5.2.2.
Column Packet (COLC/COLX).................................................................. 106
5.2.2.1.
Data Packet .................................................................................. 107
Direct RDRAM Register Programming........................................................................ 107
Direct RDRAM Operating States ................................................................................. 108
RDRAM Operating Pools............................................................................................. 109
5.5.1.
Pool “A”, Pool “B”, and Pool “C” Operation ............................................... 109
RDRAM Power Management ...................................................................................... 109
Data Integrity ............................................................................................................... 110
RDRAM Array Thermal Management ......................................................................... 110
5.
Memory Interface Description .................................................................................................... 99
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
6.
Electrical Characteristics.......................................................................................................... 111
6.1.
6.2.
6.3.
6.4.
6.5.
Absolute Maximum Ratings......................................................................................... 111
Thermal Characteristics .............................................................................................. 112
Power Characteristics ................................................................................................. 112
I/O Interface Signal Groupings .................................................................................... 113
DC Characteristics ...................................................................................................... 115
7.
Pinout and Package Information.............................................................................................. 119
7.1.
7.2.
7.3.
Ballout Information ...................................................................................................... 119
Package Information ................................................................................................... 128
MCH RSL Package Dimensions ................................................................................. 129
7.3.1.
Memory Control Hub (MCH) RSL Compensation and Normalized Trace
Length Data ................................................................................................. 130
7.3.2.
Memory Controller Hub (MCH) System Bus Signal Normalized Trace Length
Data
...................................................................................................... 131
XOR Test Mode Initialization ....................................................................................... 134
XOR Chains ................................................................................................................ 134
8.
Testability ................................................................................................................................. 133
8.1.
8.2.
Datasheet
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