82442FX datasheet, PDF - EEWORLD Datasheet

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82442FX: DescriptionMicroprocessor Circuit, CMOS, PQFP208, PLASTIC, QFP-208; CategoryThe embedded processor and controller Microcontrollers and processors; File Size406KB，69 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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82442FX Overview

Microprocessor Circuit, CMOS, PQFP208, PLASTIC, QFP-208

82442FX Parametric

Parameter Name	Attribute value
Maker	Intel
Parts packaging code	QFP
package instruction	PLASTIC, QFP-208
Contacts	208
Reach Compliance Code	compliant
JESD-30 code	S-PQFP-G208
length	28 mm
Number of terminals	208
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Certification status	Not Qualified
Maximum seat height	4.25 mm
surface mount	YES
technology	CMOS
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	28 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR CIRCUIT

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PRELIMINARY

INTEL 440FX PCISET

82441FX PCI AND MEMORY CONTROLLER

(PMC) AND 82442FX DATA BUS

ACCELERATOR (DBX)

Supports the Pentium

Pro Processors

at Bus Frequencies Up To 66 Mhz



Supports 32-Bit Addressing



Optimized in-Order and Request

Queue



Full Symmetric Multi-Processor

(SMP) Protocol for up to Two

Processors



Dynamic Deferred Transaction

Support



GTL+ Compliant Host Bus



Supports USWC Cycles

Integrated DRAM Controller



8 MB to 1 GB Main Memory



64/72-Bit Non-Interleaved Path to

Memory



FPM (Fast Page Mode), EDO

(Extended Data Out -Page Mode),

BEDO (Extended Data Out -Burst

Mode) DRAMs Providing x-222 to

x-4-4-4 Burst Capability



Support for Auto Detection of

Memory Type: BEDO, EDO or FPM



8 RAS Lines Available



Support for 4-, 16- and 64-Mb DRAM

Devices



Support for Symmetrical and

Asymmetrical DRAM Addressing



Configurable Support for ECC or

Parity



ECC with Single Bit Error

Correction and Multiple Bit Error

Detection



Read-Around-Write Support for

Host and PCI DRAM Read Accesses



Supports 3.3V or 5V DRAMs

PCI Bus Interface



PCI Rev. 2.1, 5V Interface Compliant



Greater than 100 MBps Data

Streaming for PCI to DRAM

Accesses Enables Native Signal

Processing (NSP) on Systems

Designed With the Pentium Pro

Processor



Integrated Arbiter With Multi-

Transaction PCI Arbitration

Accelerator Hooks



5 PCI Bus Masters are Supported in

Addition to the Host and PCI-to-ISA

I/O Bridge



Delayed Transaction Support



PCI Parity Checking and Generation

Support



Supports Concurrent Pentium Pro

and PCI Transactions to Main

Memory

Data Buffering For Increased

Performance



Extensive CPU-to-DRAM and PCI-

to-DRAM Write Data Buffering



Write Combining Support for CPU-

to-PCI Burst Writes

System Management Mode (SMM)

Compliant

208-Pin PQFP PCI Bridge/ Memory

Controller (PMC), 208-Pin PQFP for the

440FX PCIset Data Bus Accelerator

(DBX)

The Intel 440FX PCIset provides a highly integrated solution for systems based on one or two Pentium

Pro

processors. The 440FX PCIset consists of the 82441FX PCI and Memory Controller (PMC), the 82442FX Data

Bus Accelerator (DBX), and the 82371SB PCI I/O IDE Xcelerator (PIIX3). The PMC and DBX provide a two-chip

host-to-PCI bridge including the DRAM control function, the PCI interface, and the PCI arbiter function. The

440FX PCIset supports EDO, FPM, and BEDO DRAM technologies. The DRAM controller provides support for

up to eight rows of memory and optional DRAM error detection/correction or parity. The 440FX PCIset contains

extensive buffering between all interfaces for high system data throughput and concurrent operations.

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights

is granted by this document or by the sale of Intel products. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a

particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life

saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The Intel 440FX

PCIset may contain design defects or errors known as errata. Current characterized errata are available on request. Third-party brands and names are the property

of their respective owners.

May 1996

Order Number: 290549-001

82441FX (PMC) AND 82442FX (DBX)

CONTENTS

PAGE

1.0. OVERVIEW ......................................................................................................................................................6

2.0. SIGNAL DESCRIPTION ..................................................................................................................................8

2.1. PMC Signals .................................................................................................................................................9

2.1.1. HOST INTERFACE (PMC)....................................................................................................................9

2.1.2. DRAM INTERFACE (PMC) .................................................................................................................10

2.1.3. PCI INTERFACE (PMC)......................................................................................................................11

2.1.4. PCI SIDEBAND INTERFACE (PMC) ..................................................................................................12

2.1.5. DBX INTERFACE (PMC) ....................................................................................................................13

2.1.6. CLOCKS (PMC)...................................................................................................................................13

2.1.7. MISCELLANEOUS (PMC)...................................................................................................................13

2.1.8. POWER UP STRAP OPTIONS (PMC) ...............................................................................................14

2.2. DBX Signals................................................................................................................................................15

2.2.1. DRAM INTERFACE SIGNALS (DBX).................................................................................................15

2.2.2. PMC INTERFACE SIGNALS (DBX)....................................................................................................15

2.2.3. HOST INTERFACE SIGNALS (DBX) .................................................................................................15

2.2.4. MISCELLANEOUS (DBX) ...................................................................................................................16

2.2.5. POWER UP STRAP OPTIONS (DBX)................................................................................................16

3.0. REGISTER DESCRIPTION ...........................................................................................................................17

3.1. I/O Mapped Registers .................................................................................................................................17

3.1.1. CONFADDCONFIGURATION ADDRESS REGISTER ..................................................................18

3.1.2. CONFDATACONFIGURATION DATA REGISTER ........................................................................18

3.2. PCI Configuration Space Mapped Registers ..............................................................................................19

3.2.1. PCI CONFIGURATION ACCESS .......................................................................................................19

3.2.2. VIDVENDOR IDENTIFICATION REGISTER..................................................................................21

3.2.3. DIDDEVICE IDENTIFICATION REGISTER....................................................................................21

3.2.4. PCICMDPCI COMMAND REGISTER .............................................................................................21

3.2.5. PCISTSPCI STATUS REGISTER ...................................................................................................22

3.2.6. RIDREVISION IDENTIFICATION REGISTER................................................................................23

3.2.7. CLASSCCLASS CODE REGISTER................................................................................................23

3.2.8. MLTMASTER LATENCY TIMER REGISTER .................................................................................24

3.2.9. HEADTHEADER TYPE REGISTER................................................................................................24

3.2.10. BISTBIST REGISTER....................................................................................................................24

3.2.11. PMCCFGPMC CONFIGURATION REGISTER ............................................................................25

3.2.12. DETURBODETURBO COUNTER REGISTER.............................................................................26

3.2.13. DBCDBX BUFFER CONTROL......................................................................................................26

3.2.14. AXCAUXILIARY CONTROL REGISTER ......................................................................................27

3.2.15. DRT

DRAM

ROW TYPE REGISTER ............................................................................................28

3.2.16. DRAMCDRAM CONTROL REGISTER.........................................................................................28

3.2.17. DRAMT

DRAM

TIMING REGISTER .............................................................................................29

3.2.18. PAMPROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM[6:0])..........................................30

3.2.19. DRB[0:7]

DRAM

ROW BOUNDARY REGISTERS .......................................................................32

PRELIMINARY

82441FX (PMC) AND 82442FX (DBX)

3.2.20. FDHCFIXED DRAM HOLE CONTROL REGISTER ....................................................................33

3.2.21. MTTMULTI-TRANSACTION TIMER REGISTER..........................................................................34

3.2.22. CLTCPU LATENCY TIMER REGISTER .......................................................................................34

3.2.23. SMRAMSYSTEM MANAGEMENT RAM CONTROL REGISTER ................................................35

3.2.24. ERRCMDERROR COMMAND REGISTER ..................................................................................36

3.2.25. ERRSTSERROR STATUS REGISTER ........................................................................................37

3.2.26. TRCTURBO RESET CONTROL REGISTER ...............................................................................38

4.0. FUNCTIONAL DESCRIPTION ......................................................................................................................39

4.1. System Address Map..................................................................................................................................39

4.1.1. MEMORY ADDRESS RANGES..........................................................................................................39

4.1.1.1. Compatibility Area .........................................................................................................................40

4.1.1.2. Extended Memory Area ................................................................................................................41

4.1.2. SYSTEM MANAGEMENT MODE (SMM) MEMORY RANGE............................................................42

4.1.3. MEMORY SHADOWING.....................................................................................................................42

4.1.4. I/O ADDRESS SPACE ........................................................................................................................42

4.2. Host Interface..............................................................................................................................................42

4.3. DRAM Interface ..........................................................................................................................................43

4.3.1. DRAM POPULATION RULES.............................................................................................................43

4.3.2. AUTO-DETECTION.............................................................................................................................45

4.3.3. DRAM ADDRESS TRANSLATION AND DECODING .......................................................................46

4.3.4. PSEUDO-ALGORITHM FOR DYNAMIC MEMORY SIZING .............................................................47

4.3.5. DATA INTEGRITY SUPPORT ............................................................................................................48

4.3.5.1. Software Requirements.................................................................................................................48

4.3.5.2. Parity Detection.............................................................................................................................48

4.3.5.3. Error Detection and correction ......................................................................................................49

4.3.5.4. ECC/Parity Test Mode ..................................................................................................................52

4.4. PCI Bus Arbitration .....................................................................................................................................53

4.5. System Clocking and Reset........................................................................................................................54

4.5.1. HOST FREQUENCY SUPPORT ........................................................................................................54

4.5.2. CLOCK GENERATION AND DISTRIBUTION....................................................................................54

4.5.3. SYSTEM RESET .................................................................................................................................54

4.5.3.1. Hard Reset ....................................................................................................................................55

4.5.3.2. Soft Reset .....................................................................................................................................57

4.5.3.3. CPU BIST......................................................................................................................................57

5.0. PINOUT AND PACKAGE SPECIFICATIONS ..............................................................................................58

5.1. PMC Pinout Information ..............................................................................................................................58

5.2. DBX Pinout Information...............................................................................................................................62

5.3. PMC & DBX Package Specifications..........................................................................................................66

6.0. TESTABILITY.................................................................................................................................................67

6.1. 82441FX (PMC) Test Modes ......................................................................................................................67

6.2. DBX Test Mode...........................................................................................................................................68

PRELIMINARY

82442FX Related Products

	82442FX	82441FX
Description	Microprocessor Circuit, CMOS, PQFP208, PLASTIC, QFP-208	PCI Bus Controller, CMOS, PQFP208, PLASTIC, QFP-208
Maker	Intel	Intel
Parts packaging code	QFP	QFP
package instruction	PLASTIC, QFP-208	FQFP,
Contacts	208	208
Reach Compliance Code	compliant	compliant
JESD-30 code	S-PQFP-G208	S-PQFP-G208
length	28 mm	28 mm
Number of terminals	208	208
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	FQFP	FQFP
Package shape	SQUARE	SQUARE
Package form	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH
Certification status	Not Qualified	Not Qualified
Maximum seat height	4.25 mm	4.25 mm
surface mount	YES	YES
technology	CMOS	CMOS
Terminal form	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
width	28 mm	28 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR CIRCUIT	BUS CONTROLLER, PCI

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