ST7L38MA/XXXTRE datasheet, PDF - EEWORLD Datasheet

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ST7L38MA/XXXTRE: DescriptionIC,MICROCONTROLLER,8-BIT,ST7 CPU,CMOS,SOP,20PIN,PLASTIC; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，236 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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ST7L38MA/XXXTRE Overview

IC,MICROCONTROLLER,8-BIT,ST7 CPU,CMOS,SOP,20PIN,PLASTIC

ST7L38MA/XXXTRE Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Reach Compliance Code	compliant
Has ADC	YES
Address bus width
bit size	8
CPU series	ST7
maximum clock frequency	16 MHz
DMA channel	NO
External data bus width
JESD-30 code	R-PDSO-G20
length	12.8 mm
Number of I/O lines	15
Number of terminals	20
On-chip program ROM width	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	3.3/5 V
Certification status	Not Qualified
RAM (bytes)	384
rom(word)	8192
ROM programmability	MROM
speed	16 MHz
Maximum slew rate	9 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	3.3 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	7.5 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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ST7L34, ST7L35

ST7L38, ST7L39

8-bit MCU for automotive with single voltage Flash/ROM,

data EEPROM, ADC, timers, SPI, LINSCI™

Features

■

Memories

– 8 Kbytes program memory: Single voltage

extended Flash (XFlash) or ROM with

readout protection capability. In-application

programming and in-circuit programming

(IAP and ICP) for XFlash devices

– 384 bytes RAM

– 256 bytes data EEPROM (XFlash and

ROM devices) with readout protection, 300

K write/erase cycles guaranteed

– XFlash and EEPROM data retention

20 years at 55°C

Clock, reset and supply management

– Enhanced reset system

– Enhanced low voltage supervisor (LVD) for

main supply and an auxiliary voltage

detector (AVD) with interrupt capability for

implementing safe power-down procedures

– Clock sources: Internal 1% RC oscillator,

crystal/ceramic resonator or external clock

– Optional x8 PLL for 8 MHz internal clock

– 5 power saving modes: Halt, active halt,

auto wakeup from halt, wait and slow

I/O ports

– Up to 15 multifunctional bidirectional I/O

lines

– 7 high sink outputs

5 timers

– Configurable watchdog timer

– Two 8-bit lite timers with prescaler, 1 real-

time base and 1 input capture

– Two 12-bit autoreload timers with 4 PWM

outputs, 1 input capture and 4 output

compare functions

SO20

300 mil

QFN20

■

2 communication interfaces

– Master/slave LINSCI™ asynchronous

serial interface

– SPI synchronous serial interface

Interrupt management

– 10 interrupt vectors plus TRAP and reset

– 12 external interrupt lines (on 4 vectors)

A/D converter

– 7 input channels

– 10-bit resolution

Instruction set

– 8-bit data manipulation

– 63 basic instructions with illegal opcode

detection

– 17 main addressing modes

– 8 x 8 unsigned multiply instructions

Development tools

– Full hardware/software development

package

– DM (debug module)

■

■

■

■

■

■

■

October 2010

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1

Contents

ST7L34, ST7L35, ST7L38, ST7L39

Contents

1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.1

1.2

Parametric data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Debug module (DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2

3

4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1

4.2

4.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.1

4.3.2

In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.4

4.5

ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.5.1

4.5.2

Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.6

4.7

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5

Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1

5.2

5.3

5.4

5.5

5.6

5.7

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Data EEPROM readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6

Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.1

6.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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Contents

6.3

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7

Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.1

7.2

7.3

7.4

Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.4.1

7.4.2

7.4.3

External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.5

Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.5.1

7.5.2

7.5.3

7.5.4

7.5.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 45

Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.6

System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.6.1

7.6.2

7.6.3

7.6.4

Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.1

8.2

8.3

Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9.1

9.2

9.3

9.4

9.5

9.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.4.1

Halt mode recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Auto wakeup from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

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ST7L34, ST7L35, ST7L38, ST7L39

10

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.1

10.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.2.1

10.2.2

10.2.3

Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

10.3

10.4

10.5

10.6

10.7

I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Device-specific I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

11

On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

11.1

Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

11.1.1

11.1.2

11.1.3

11.1.4

11.1.5

11.1.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

11.2

Dual 12-bit autoreload timer 3 (AT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

11.2.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

11.3

Lite timer 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

11.3.1

11.3.2

11.3.3

11.3.4

11.3.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

11.4

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.4.1

11.4.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

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ST7L34, ST7L35, ST7L38, ST7L39

11.4.3

11.4.4

11.4.5

11.4.6

11.4.7

11.4.8

Contents

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

11.5

LINSCI serial communication interface (LIN master/slave) . . . . . . . . . . 123

11.5.1

11.5.2

11.5.3

11.5.4

11.5.5

11.5.6

11.5.7

11.5.8

11.5.9

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

SCI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

LIN features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SCI mode - functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

SCI mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

LIN mode - functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

11.5.10 LIN mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

11.6

10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

11.6.1

11.6.2

11.6.3

11.6.4

11.6.5

11.6.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

12

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

12.1

ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

12.1.1

12.1.2

12.1.3

12.1.4

12.1.5

12.1.6

12.1.7

Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

12.2

Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

12.2.1

12.2.2

Using a prebyte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Doc ID 11928 Rev 7

5/236

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