®
CMOS ST-BUS™ FAMILY
MT8910-1
Digital Subscriber Line Interface Circuit
Preliminary Information
Features
•
•
•
•
•
•
•
•
•
•
•
•
Compatible with ISDN U-Interface standard
Over 40dB (
@
40 kHz) of loop attenuation
Full duplex transmission over single twisted
pair
Advanced echo cancelling technology
High performance 2B1Q line code
Full activation/deactivation state machine
QSNR and line attenuation diagnostics
Frame and superframe synchronization
On-chip 15 second timer
Insertion loss measurement test signal & quiet
mode
Mitel ST-BUS compatible
Single 5V power supply
ISSUE 1
August 1993
Ordering Information
MT8910-1AC 28 Pin Ceramic DIP
MT8910-1AP
44 Pin PLCC
0°C to +70°C
Description
The MT8910-1 Digital Subscriber Line Interface
Circuit (DSLIC) is designed to provide ISDN basic
rate access (2B+D) at the U-interface. Full duplex
digital transmission at 160 kbit/s on a single twisted
pair is achieved using echo cancelling hybrid (ECH)
technology.
This, in conjunction with the high
performance 2B1Q line code, allows the DSLIC to
meet the loop length requirements of the digital
subscriber loops at the U-interface over the entire
non-loaded telephone loop plant.
The MT8910-1 is compatible with the complete
range of Mitel Semiconductor ISDN components
through the use of the ST-BUS interface.
Applications
•
•
•
•
ISDN NT1 and NT2 DSL interface
Digital PABX line cards and telephone sets
Digital multiplexers and concentrators
Pair gain system
DSTi
CDSTi
Transmit
Interface
Scrambler
& Encoder
DAC and
Tx Filter
+
Lout+
MRST
F0b
C4b
SFb
F0od
MS0
MS1
NT/LT
Control
Register
Jitter
Compen-
sator
Linear
Echo
Canceller
Non-
Linear
Compen-
sator
-
Lout-
Tone
Detector
TRANSMIT/
RECEIVE TIMING
& CONTROL
INTERFACE
Framing
&
Maintenance
Decision
Feedback
Equalizer
2nd Order
PDM ADC
Status
Register
Quantizer
FIR
Digital Filter
CDSTo
DSTo
Receive
Interface
Descrambler,
Decoder &
Diagnostics
Timing
Adaptation
Circuit
Bias &
Voltage Ref.
Lin+
Lin-
VSS
AVSS
VDD
AVDD
OSC2
OSC1
TSTin
TSTout TSTen VRef
VBias
Figure 1 - Functional Block Diagram
9-3
MT8910-1
Preliminary Information
TSTin
AVSS
NC
Lout+
NC
Lout-
Lin+
Lin-
VRef
VBias
NC
28 PIN CERDIP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
DIP PLCC
1
2
3
4
1
3
5
6
L
out-
L
out+
AV
SS
TSTin
Line Out Minus.
One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q
signal, biased at V
Bias
.
Line Out Plus.
One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q signal,
biased at V
Bias
.
Analog Ground.
Tie to V
SS
.
I/O Structure Test Input.
When TSTen is high, TSTin is used as a source to all output
drivers. Refer to “I/O Structure Test" in functional description for more details. Tie to V
SS
for normal operation.
Description
5
6
7
8
8
12
13
14
CDSTi
Control/Data ST-BUS Input.
A 2048 kbit/s serial PCM/data input for the D- and
C-channels in Dual mode. Unused in Single mode and should be connected to V
SS
.
DSTi
V
SS
DSTo
Data ST-BUS Input.
A 2048 kbit/s serial PCM/data input for the D-, C-, B1- and B2-
channels in Single mode. In Dual mode, only the B-channels are input.
Ground.
Data ST-BUS Output.
A 2048 kbit/s serial PCM/data output for the D-, C-, B1- and B2-
channels in Single mode. In Dual mode, only the B-channels are output. This output is
placed in high impedance during the unused channel times.
9
15
CDSTo
Control/Data ST-BUS Output.
A 2048 kbit/s serial PCM/data output for the D- and
C- channels in Dual mode. It is placed in high impedance in Single mode, and during the
unused channel times in Dual mode.
F0od
Delayed Frame Pulse Output.
A 244 ns wide negative going pulse indicating the end of
the active ST-BUS channel times of the device to allow for daisy-chaining of other ST-BUS
devices. Active after channel 0 in Dual Port mode and Channel 3 in Single Port Mode.
10
16
11
18
TSTout
I/O Structure Test Output.
When TSTen is high, the TSTout provides the output of an
XOR chain which is sourced from all digital inputs. Refer to “I/O Structure Test" in
functional description for more details. Leave unconnected for normal operation.
MS0
MS1
Mode Select 0.
CMOS input. Refer to Table 1.
Mode Select 1.
CMOS input. Refer to Table 1.
12
13
9-4
19
20
TSTout
MS0
MS1
NT/LT
TSTen
SFb
NC
C4b
NC
F0b
NC
44 PIN PLCC
Lout-
Lout+
AVSS
TSTin
CDSTi
DSTi
VSS
DSTo
CDSTo
F0od
TSTout
MS0
MS1
NT/LT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Lin+
Lin-
VRef
VBias
AVDD
IC
VDD
MRST
OSC1
OSC2
F0b
C4b
SFb
TSTen
NC
CDSTi
NC
NC
NC
DSTi
VSS
DSTo
CDSTo
F0od
NC
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
NC
AVDD
NC
NC
NC
IC
VDD
MRST
OSC1
OSC2
NC
Preliminary Information
Pin Description (continued)
Pin #
Name
DIP PLCC
14
15
21
22
NT/LT
TSTen
Description
MT8910-1
NT/LT Mode Select.
CMOS Input. When high, the DSLIC is setup in NT mode. When
low, LT mode is selected.
I/O Structure Test Enable Input.
This active high input enables the built-in test of all
digital input and output structures. Refer to “I/O Structure Test" in functional description for
more details. Tie to V
SS
for normal operation.
Superframe Pulse.
In LT mode, an input pulse once every superframe (12 ms) which,
when low during a falling edge of C4b within an F0b low pulse, sets the transmit
superframe boundary.
In NT mode, a 244 ns wide output pulse once every 12 ms indicating the boundary of the
transmit superframe. In NT mode, the superframe timing is generated from the line signal
time base and, as such, SFb will only be valid once the transceiver has achieved full
activation.
16
23
SFb
17
18
25
27
C4b
F0b
4096 kHz Data Clock.
In LT mode, a 4096 kHz ST-BUS clock input. In NT mode, a 4096
kHz ST-BUS clock output frequency locked to the line signal.
Frame Pulse.
In LT mode, an 8 kHz input pulse indicating the start of the active ST-BUS
channel times. In NT mode, an 8 kHz output pulse extracted from the line signal indicating
the start of the active ST-BUS channel times.
Oscillator Output.
When the MT8910-1 operates with an External Clock (typically LT
mode) connect OSC2 to the output of an external inverter providing a 10.24 MHz ±5ppm
clock (see “10.24 MHz Clock Interface" section).
When operating with a crystal (typically NT mode) connect one lead of the fundamental
mode parallel resonator crystal (10.24 MHz ±50ppm in case of NT mode).
19
30
OSC2
20
31
OSC1
Oscillator Input.
When the DSLIC operates with an External Clock (typically LT mode)
connect OSC1 to the input of an external inverter (see Fig.11).
When operating with a crystal (typically NT mode) connect the other lead of the
fundamental mode parallel resonator crystal (10.24 MHz ±50ppm in case of NT mode).
21
22
23
24
25
26
27
28
32
33
34
38
41
42
43
44
2,4,7,
9 -11,
17,24
26,28
29,35
36,37
39,40
MRST
V
DD
IC
AV
DD
V
Bias
V
Ref
L
in-
L
in+
NC
Master Reset.
Active low CMOS input performs a master reset of the DSLIC.
Power Supply Input.
Internal Connection.
Leave unconnected.
Analog Power Supply.
Connect to V
DD
.
Bias Voltage.
Decouple to AV
SS
through a 1.0 µF ceramic capacitor.
Reference Voltage.
Decouple to AV
SS
through a 1.0 µF ceramic capacitor.
Line Signal Input Minus.
Internally biased at V
Bias.
Line Signal Input Plus.
Internally biased at V
Bias.
No Connection.
Leave circuit open.
9-5
MT8910-1
Functional Description
The MT8910-1 Digital Subscriber Line Interface
Circuit (DSLIC) is a high performance, full duplex
transceiver which provides a complete interface to
the U-reference point as specified in ANSI T1.601-
1988. Operating in either master Line Terminator
(LT) mode or slave Network Terminator (NT) mode,
the DSLIC can be configured to operate at either end
of the Digital Subscriber Line (DSL). The DSLIC
supports full duplex transmission of a 2B + D-
channel format at 160 kbit/s over a single twisted
pair with about 40 dB of loop attenuation at 40 kHz.
To achieve this transmission performance, the
DSLIC uses a 2B1Q line code which is a four level
pulse amplitude modulated (PAM) signal with no
redundancy. This line code was approved by the
American National Standards Institute technical
committee T1E1. Using this line code, two binary
bits are converted into one four level quaternary
symbol. This results in an effective baud rate
reduction from 160 to 80 kbaud/s allowing the
transmission to benefit from reduced line attenuation
and improved immunity to near end crosstalk
(NEXT).
To complement the performance of the 2B1Q line
code, the DSLIC uses an advanced echo cancelling
hybrid (ECH) technique, by means of a transversal
filter, that provides greater than 60 dB of echo
cancellation.
This cancellation, along with all
equalization, is performed in the digital domain using
dedicated DSP hardware. Since a digital transversal
echo canceller gives a linear representation of the
echo, the MT8910-1 also has a non-linear echo
canceller which works in parallel with the transversal
filter to compensate for non-linearities in the transmit
path and the passive line termination. In addition, a
jitter compensator is used to correct errors in the
echo estimates which are sourced from corrections
in the received timebase. The jitter compensator will
interact directly with the echo taps in the transversal
filter.
A block diagram of the DSLIC is shown in Figure 1.
The DSLIC has two ports consisting of a serial
system interface (Mitel's standard ST-BUS), and a
line port which interfaces directly to the single
twisted pair via a passive termination hybrid and a
line pulse transformer.
The two B-channels and the D-channel to be
transmitted on the line are input to the DSLIC (on the
ST-BUS) into the transmit interface block. The sync
word and maintenance bits are added to the data
which is then formatted, scrambled and digitally
encoded into 2B1Q symbols.
This digital
representation is passed through a finite impulse
9-6
Preliminary Information
response filter which converts the digital
representation into an analog waveform. The
transmitted pulse is then passed through a
smoothing filter whose output is passed to a
differential line driver which is driving the line through
a passive hybrid network and line pulse transformer.
On the receive side, the pre-cancelled signal drives
a balanced receiver which feeds the input to an over-
sampled second-order delta sigma A/D converter.
The digital representation of the received signal
yields a Pulse Density Modulated (PDM) stream
which is digitally filtered and decimated to the 80 kHz
baseband. Intersymbol interference (ISI) introduced
by the loop is cancelled by a decision feedback
equalizer. This is achieved by taking a convolution
of the received pulse with the estimated impulse
response of the loop. The cancellation of ISI is
performed in parallel with the echo cancellation.
Estimated received echo is obtained by taking the
convolution of the transmit signal with the estimated
impulse response of the loop. Feedback from the
jitter compensator and the non-linear corrector
interact with the coefficients of the echo canceller to
reduce the error introduced by jitter and non-
linearities in the analog circuitry. The output of all
these blocks is summed together and the result is
the received data which is passed through a decoder
and descrambler before being sent out in TDM
bursts on the ST-BUS.
Line Port
The DSLIC interfaces to the U-reference point as
defined in the ISDN Basic Access Reference model.
As such, the transceiver transfers full duplex, time
division multiplexed data at 160 kbit/s. This includes
two 64 kbit/s PCM voice or data channels (B-
channels), a 16 kbit/s signalling channel (D-channel)
and 16 kbit/s for synchronization and overhead.
The two 64 kbit/s channels are defined as the B1-
and B2-channels and they carry subscriber
information such as digitally encoded voice, circuit
switched data or packet switched data. The DSLIC
will transfer both B-channels transparently from the
ST-BUS port to the line port and vice versa once the
device has acquired superframe synchronization.
The 16 kbit/s D-channel is primarily intended to carry
signalling information for circuit switching the B-
channels through the ISDN network. The D-channel
can optionally carry packetized information and
telemetry services. The D-channel is transmitted
transparently through the DSLIC from the ST-BUS
port to the line port and vice versa once the device
has acquired superframe synchronization. It is to be
Preliminary Information
noted that the system interface has dedicated a full
64 kbit/s for the D-channel of which only the two first
bits (D0 and D1) are actually carrying information.
The other bits of the ST-BUS D-channel are reserved
for future use.
A third type of channel, the C-channel, is a non-
bearer channel which provides a means for the
system to control and monitor the functionality of the
DSLIC. This control/status channel is accessed by
the system through the ST-BUS. The C-channel
provides access to three control registers and four
status registers which provide complete control or
status of all built-in features. Access to the control
register is provided by two bits in the Control
Register itself (CRS0 and CRS1). Selection of the
desired status register is performed using two bits in
Control Register 1 (SRS0 and SRS1).
The C-
channel also carries a control and status register for
the 4 kbit/s M-channel which can be used as an
additional maintenance channel.
A detailed
description of these registers is discussed in the ST-
BUS port interface section.
Line Code
The DSLIC transceiver uses the 2B1Q line code
which is a four level Pulse Amplitude Modulated
(PAM) code with no redundancy. The generation of
the 2B1Q signal is achieved by grouping two
consecutive bits into a bit field of which the first bit
represents the sign bit and the second represents
the magnitude. This yields four possible output
codes as shown in Figure 3 (note that +3, +1, -1 and
-3 are only symbols and they do not reflect the
voltage on the line).
The bit fields are grouped relative to the borders of
the defined channels where the first bit field consists
of bit 1 and bit 2 of the B1-channel, the second bit
field consists of bit 3 and bit 4 of the B1-channel
and so on.
MT8910-1
Before converting the bit fields into output symbols,
all bits except the framing pattern are scrambled with
polynomials:
1
⊕
x
-5
⊕
x
-23
for LT
1
⊕
x
-18
⊕
x
-23
for NT
(where
⊕
is modulo two summation)
Framing
The frame structure in the DSLIC is 1.5 ms long and
consists of twelve 2B+D-channels delimited by the
framing pattern at the start of the frame and the
maintenance channel at the end. Framing for both
the LT and the NT is performed using a 9 symbol
synchronization word. This sync word (SW) has the
following structure:
Sync Word: +3, +3, -3, -3, -3, +3, -3, +3, +3
Eight DSLIC frames are grouped into a superframe
delimited by inverting the sync word (ISW):-3,-3, +3,
+3, +3, -3, +3, -3, -3. This second level of framing is
used to assign the M-channel bits as defined in the
ANSI T1.601-1988. The framing structure is shown
in Figure 4.
Transmission between the LT and NT is fully
synchronous.
As such, the frame/superframe
boundaries between the NT receive frame and the
NT transmit frame have a fixed phase relationship.
The transmitted frame/superframe from the NT is
delayed by 60 ± 2 quaternary symbols (quats) with
respect to its received frame/superframe. Since the
NT extracts all its timing from the line, the DSLIC will
maintain the required phase relationship between
the frames and superframes and will insert the SW
and ISW during the proper time interval.
+3
+1
-1
-3
time
QUATS
-1 +3
BITS
0 1 1 0
+1
1 1
-3
0 0
-3
0 0
+1
1 1
+3
1 0
-3
0 0
-1
0 1
-1
0 1
+1
1 1
-1
0 1
-3
0 0
+3
1 0
+3
1 0
-1
0 1
+1
1 1
Figure 3 - Example of 2B1Q Quaternary Symbols
9-7
京公网安备 11010802033920号
EEWORLD
