NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
Connection Diagrams
DIP PIN CONFIGURATIONS
27C080
27C040
27C020 27C512 27C256
DIP
NM27C010
XX/V
PP
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
27C256
27C512
27C020
27C040
27C080
A
19
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
XX/V
PP
XX/V
PP
A
16
A
16
A
15
A
15
A
15
A
12
A
12
A
12
A
7
A
7
A
7
A
6
A
6
A
6
A
5
A
5
A
5
A
4
A
4
A
4
A
3
A
3
A
3
A
2
A
2
A
2
A
1
A
1
A
1
A
0
A
0
A
0
O
0
O
0
O
0
O
1
O
1
O
1
O
2
O
2
O
2
GND
GND GND
V
PP
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
V
CC
V
CC
V
CC
V
CC
XX/PGM
A
18
A
18
XX/PGM
A
17
V
CC
V
CC
A
17
A
17
XX
A
14
A
14
A
14
A
14
A
14
A
14
A
13
A
13
A
13
A
13
A
13
A
13
A
8
A
8
A
8
A
8
A
8
A
8
A
9
A
9
A
9
A
9
A
9
A
9
A
11
A
11
A
11
A
11
A
11
A
11
OE
OE/V
PP
OE
OE/V
PP
OE
OE
A
10
A
10
A
10
A
10
A
10
A
10
CE/PGM CE/PGM
CE
CE/PGM CE/PGM
CE
O
7
O
7
O
7
O
7
O
7
O
7
O
6
O
6
O
6
O
6
O
6
O
6
O
5
O
5
O
5
O
5
O
5
O
5
O
4
O
4
O
4
O
4
O
4
O
4
O
3
O
3
O
3
O
3
O
3
O
3
DS010798-10
Note:
Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C010 pins.
Commercial Temperature Range
(0°C to +70°C) V
CC
= 5V
±10%
Parameter/Order Number
NM27C010 Q, V, N 70
NM27C010 Q, V, N 90
NM27C010 Q, V, N 120
NM27C010 Q, V, N 150
Package Types: NM27C010 Q, N, V XXX
Q = Quartz-Windowed Ceramic DIP package
V = PLCC package
N = Plastic DIP package
• All packages conform to JEDEC standard.
• All versions are guaranteed to function at slower speeds.
Extended Temperature Range
(-40°C to +85°C) V
CC
= 5V
±10%
Parameter/Order Number
NM27C010 QE, VE, NE 70
NM27C010 QE, VE, NE 90
NM27C010 QE, VE, NE 120
NM27C010 QE, VE, NE 150
Access Time (ns)
70
90
120
150
Access Time (ns)
70
90
120
150
Pin Names
A0–A16
CE
OE
O0–O7
PGM
XX
Addresses
Chip Enable
Output Enable
Outputs
Program
Don’t Care (During Read)
PLCC Pin Configuration
A
12
A
15
A
16
XX/V
PP
V
CC
XX/PGM
XX
4
3
2
1 32 31 30
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
29
28
27
26
25
24
23
22
21
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
O
7
O
1
O
2
GND
O
3
O
4
O
5
O
6
Top View
DS010798-3
2
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NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
Absolute Maximum Ratings
(Note 1)
Storage Temperature
All Input Voltages Except A9 with
Respect to Ground (Note 10)
V
PP
and A9 with Respect to Ground
V
CC
Supply Voltage with
Respect to Ground
ESD Protection
-65°C to +150°C
All Output Voltages with
Respect to Ground (Note 10)
V
CC
+ 1.0V to GND - 0.6V
Operating Range
-0.6V to +7V
-0.6V to +14V
-0.6V to +7V
>2000V
Range
Commercial
Extended
Temperature
0°C to +70°C
-40°C to +85°C
V
CC
+5V
+5V
Tolerance
±10%
±10%
DC Read Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
V
IL
V
IH
V
OL
V
OH
I
SB1
I
SB2
I
CC
I
PP
V
PP
I
LI
I
LO
Parameter
Input Low Level
Input High Level
Output Low Voltage
Output High Voltage
V
CC
Standby Current
(CMOS)
V
CC
Standby Current (TTL)
V
CC
Active Current
V
PP
Supply Current
V
PP
Read Voltage
Input Load Current
Output Leakage Current
Test Conditions
Min
-0.5
2.0
Max
0.8
V
CC
+1
0.4
Units
V
V
V
V
I
OL
= 2.1 mA
I
OH
= -2.5 mA
CE = V
CC
±
0.3V
CE = V
IH
CE = OE = V
IL
I/O = 0 mA
V
PP
= V
CC
V
CC
- 0.7
V
IN
= 5.5 or GND
V
OUT
= 5.5V or GND
-1
-10
f = 5 MHz
3.5
100
1
30
10
V
CC
1
10
µA
mA
mA
µA
V
µA
µA
AC Read Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
t
ACC
t
CE
t
OE
t
DF
(Note 2)
t
OH
(Note 2)
Parameter
Min
Address to Output Delay
CE to Output Delay
OE to Output Delay
Output Disable to Output
Float
Output Hold from
Addresses, CE or OE ,
Whichever Occurred First
0
70
Max
70
70
35
30
90
Min
Max
90
90
40
35
120
Min
Max
120
120
50
35
150
Min
Max
150
150
50
45
Units
ns
0
0
0
Capacitance
T
A
= +25°C, f = 1 MHz (Note 2)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
6
10
Max
15
15
Units
pF
pF
3
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NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
AC Test Conditions
Output Load
1 TTL Gate and C
L
= 100 pF (Note 8)
≤5
ns
0.45V to 2.4V
0.8V and 2V
0.8V and 2V
Input Rise and Fall Times
Input Pulse Levels
Timing Measurement Reference Level
Inputs
Outputs
AC Waveforms
(Note 6), (Note 7), and (Note 9)
ADDRESS
2V
0.8V
Address Valid
CE
2V
0.8V
t
CF
(Note 4, 5)
OE
0.8V
t
OE
(Note 3)
2V
0.8V
2V
t
CE
t
DF
(Note 4, 5)
Valid Output
OUTPUT
Hi-Z
t
ACC
(Note 3)
Hi-Z
t
OH
DS010798-4
Note 1:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2:
This parameter is only sampled and is not 100% tested.
Note 3:
OE may be delayed up to t
ACC
- t
OE
after the falling edge of CE without impacting t
ACC
.
Note 4:
The t
DF
and t
CF
compare level is determined as follows:
High to TRI-STATE
®
, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5:
TRI-STATE may be attained using OE or CE.
Note 6:
The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1
µF
ceramic capacitor be used on every device
between V
CC
and GND.
Note 7:
The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 8:
1 TTL Gate: I
OL
= 1.6 mA, I
OH
= -400
µA.
C
L
: 100 pF includes fixture capacitance.
Note 9:
V
PP
may be connected to V
CC
except during programming.
Note 10:
Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Programming Characteristics
(Note 11), (Note 12), (Note 13), and (Note 14)
Symbol
t
AS
t
OES
t
CES
t
DS
t
VPS
t
VCS
t
AH
t
DH
t
DF
t
PW
Parameter
Address Setup Time
OE Setup Time
CE Setup Time
Data Setup Time
V
PP
Setup Time
V
CC
Setup Time
Address Hold Time
Data Hold Time
Output Enable to Output Float Delay
Program Pulse Width
Conditions
Min
1
1
Typ
Max
Units
µs
µs
µs
µs
µs
µs
µs
µs
OE = V
IH
1
1
1
1
0
1
CE = V
IL
0
45
50
60
105
ns
µs
4
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NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
Programming Characteristics
(Note 11), (Note 12), (Note 13), and (Note 14) (Continued)
Symbol
t
OE
I
PP
I
CC
T
A
V
CC
V
PP
t
FR
V
IL
V
IH
t
IN
t
OUT
Parameter
Data Valid from OE
V
PP
Supply Current during
Programming Pulse
V
CC
Supply Current
Temperature Ambient
Power Supply Voltage
Programming Supply Voltage
Input Rise, Fall Time
Input Low Voltage
Input High Voltage
Input Timing Reference Voltage
Output Timing Reference Voltage
Conditions
CE = V
IL
CE = V
IL
PGM = V
IL
Min
Typ
Max
100
15
20
Units
ns
mA
mA
°C
V
V
ns
20
6.2
12.5
5
25
6.5
12.75
30
6.75
13.0
0.0
2.4
0.8
0.8
4.0
0.45
V
V
2.0
2.0
V
V
Programming Waveforms
(Note 13)
Note 11:
Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.
Program
ADDRESS
2V
0.8V
Program
Verify
Address N
t
AS
DATA
2V
0.8V
Data In Stable
ADD N
t
AH
Hi-Z
Data Out Valid
ADD N
t
DS
6.25V
t
DH
t
DF
V
CC
12.75V
t
VCS
V
PP
CE
t
VPS
0.8V
t
CES
PGM
2V
0.8V
t
PW
OE
2V
0.8V
t
OES
t
OE
DS010798-5
Note 12:
V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
. The EPROM must not be inserted into or removed from a board with
voltage applied to V
PP
or V
CC
.
Note 13:
The maximum absolute allowable voltage which may be applied to the V
PP
pin during programming is 14V. Care must be taken when switching the V
PP
supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1
µF
capacitor is required across V
PP
, V
CC
to GND to suppress spurious voltage transients
which may damage the device.
Note 14:
During power up the PGM pin must be brought high (≥V
IH
) either coincident with or before power is applied to V
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