X51638S8 datasheet, PDF - EEWORLD Datasheet

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X51638S8: Description1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, PLASTIC, SOIC-8; CategoryPower/power management The power supply circuit; File Size353KB，20 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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X51638S8 Overview

1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, PLASTIC, SOIC-8

X51638S8 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Renesas Electronics Corporation
Parts packaging code	SOIC
package instruction	PLASTIC, SOIC-8
Contacts	8
Reach Compliance Code	not_compliant
ECCN code	EAR99
Adjustable threshold	YES
Analog Integrated Circuits - Other Types	POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
Number of channels	1
Number of functions	1
Number of terminals	8
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Certification status	Not Qualified
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal location	DUAL

X51638S8 Preview

X5163, X5165

Data Sheet

May 16, 2005

FN8128.1

CPU Supervisor with 16Kbit SPI EEPROM

Description

These devices combine four popular functions, Power-on

Reset Control, Watchdog Timer, Supply Voltage Supervision,

and Block Lock Protect Serial EEPROM Memory in one

package. This combination lowers system cost, reduces

board space requirements, and increases reliability.

Applying power to the device activates the power-on reset

circuit which holds RESET/RESET active for a period of

time. This allows the power supply and oscillator to stabilize

before the processor can execute code.

The Watchdog Timer provides an independent protection

mechanism for microcontrollers. When the microcontroller

fails to restart a timer within a selectable time out interval, the

device activates the RESET/RESET signal. The user selects

the interval from three preset values. Once selected, the

interval does not change, even after cycling the power.

The device’s low V

detection circuitry protects the user’s

system from low voltage conditions, resetting the system when

falls below the minimum V

trip point. RESET/RESET is

asserted until V

returns to proper operating level and

stabilizes. Five industry standard V

TRIP

thresholds are

available, however, Intersil’s unique circuits allow the

threshold to be reprogrammed to meet custom requirements

or to fine-tune the threshold for applications requiring higher

precision.

Features

• Selectable watchdog timer

• Low V

detection and reset assertion

- Five standard reset threshold voltages

- Re-program low V

reset threshold voltage using

special programming sequence

- Reset signal valid to V

= 1V

• Determine watchdog or low voltage reset with a volatile

flag bit

• Long battery life with low power consumption

- <50µA max standby current, watchdog on

- <1µA max standby current, watchdog off

- <400µA max active current during read

• 16Kbits of EEPROM

• Built-in inadvertent write protection

- Power-up/power-down protection circuitry

- Protect 0, 1/4, 1/2 or all of EEPROM array with Block

Lock

™

protection

- In circuit programmable ROM mode

• 2MHz SPI interface modes (0,0 & 1,1)

• Minimize EEPROM programming time

- 32-byte page write mode

- Self-timed write cycle

- 5ms write cycle time (typical)

• 2.7V to 5.5V and 4.5V to 5.5V power supply operation

• Available packages

- 14-lead TSSOP, 8-lead SOIC

Pinouts

8-LEAD SOIC/PDIP

X5163, X5165

CS/WDI

X5163, X5165

RESET/RESET

SCK

14-LEAD TSSOP

X5163, X5165

CS/WDI

RESET/RESET

SCK

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X5163, X5165

Block Diagram

Watchdog Transition

Detector

SCK

CS/WDI

Data

Command

Decode &

Control

Logic

Threshold

Reset Logic

Protect Logic

RESET/RESET

Status

EEPROM Array

4K Bits

8K Bits

Reset &

Watchdog

Timebase

X5163 = RESET

X5165 = RESET

Watchdog

Timer Reset

TRIP

Power-on and

Low Voltage

Reset

Generation

Pin Description

(SOIC/PDIP)

PIN TSSOP

NAME

CS/WDI

FUNCTION

Chip Select Input.

CS HIGH, deselects the device and the SO output pin is at a high impedance

state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.

CS LOW enables the device, placing it in the active power mode. Prior to the start of any

operation after power-up, a HIGH to LOW transition on CS is required

Watchdog Input.

A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The

absence of a HIGH to LOW transition within the watchdog time out period results in

RESET/RESET going active.

Serial Output.

SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The

falling edge of the serial clock (SCK) clocks the data out.

Write Protect.

The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting

of the Watchdog Timer control and the memory write protect bits.

Ground

Serial Input.

SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this

pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),

addresses and data MSB first.

Serial Clock.

The Serial Clock controls the serial bus timing for data input and output. The rising edge

of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK

changes the data output on the SO pin.

Reset Output.

RESET/RESET is an active LOW/HIGH, open drain output which goes active

whenever V

falls below the minimum V

sense level. It will remain active until V

rises above

the minimum V

sense level for 200ms. RESET/

RESET goes active if the Watchdog Timer is enabled and CS remains either HIGH or LOW longer

than the selectable Watchdog time out period. A falling edge of CS will reset the Watchdog Timer.

RESET/RESET goes active on power-up at 1V and remains active for 200ms after the power

supply stabilizes.

Supply Voltage

No internal connections

SCK

RESET/

RESET

3-5,10-12

FN8128.1

May 16, 2005

X5163, X5165

Principles Of Operation

Power-on Reset

Application of power to the X516, /X5165 activates a Power-

on Reset Circuit. This circuit goes active at 1V and pulls the

RESET/RESET pin active. This signal prevents the system

microprocessor from starting to operate with insufficient

voltage or prior to stabilization of the oscillator. When V

exceeds the device V

TRIP

value for 200ms (nominal) the

circuit releases RESET/RESET, allowing the processor to

begin executing code.

To set the new V

TRIP

voltage, apply the desired V

TRIP

threshold to the V

pin and tie the CS/WDI pin and the WP

pin HIGH. RESET and SO pins are left unconnected. Then

apply the programming voltage V

to both SCK and SI and

pulse CS/WDI LOW then HIGH. Remove V

and the

sequence is complete.

SCK

Low Voltage Monitoring

During operation, the X5163, X5165 monitors the V

level

and asserts RESET/RESET if supply voltage falls below a

preset minimum V

TRIP

. The RESET/RESET signal prevents

the microprocessor from operating in a power fail or

brownout condition. The RESET/RESET signal remains

active until the voltage drops below 1V. It also remains active

until V

returns and exceeds V

TRIP

for 200ms.

FIGURE 1. SET V

TRIP

VOLTAGE

Watchdog Timer

The Watchdog Timer circuit monitors the microprocessor

activity by monitoring the WDI input. The microprocessor

must toggle the CS/WDI pin periodically to prevent a

RESET/RESET signal. The CS/WDI pin must be toggled

from HIGH to LOW prior to the expiration of the watchdog

time out period. The state of two nonvolatile control bits in

the Status Register determine the watchdog timer period.

The microprocessor can change these watchdog bits, or

they may be “locked” by tying the WP pin LOW and setting

the WPEN bit HIGH.

Resetting the V

TRIP

Voltage

This procedure sets the V

TRIP

to a “native” voltage level. For

example, if the current V

TRIP

is 4.4V and the V

TRIP

is reset,

the new V

TRIP

is something less than 1.7V. This procedure

must be used to set the voltage to a lower value.

To reset the V

TRIP

voltage, apply a voltage between 2.7 and

5.5V to the V

pin. Tie the CS/WDI pin, the WP pin, AND

THE SCK pin HIGH. RESET and SO pins are left

unconnected. Then apply the programming voltage V

to the

SI pin ONLY and pulse CS/WDI LOW then HIGH. Remove V

and the sequence is complete.

Threshold Reset Procedure

The X5163, X5165 has a standard V

threshold (V

TRIP

)

voltage. This value will not change over normal operating

and storage conditions. However, in applications where the

standard V

TRIP

is not exactly right, or for higher precision in

the V

TRIP

value, the X5163, X5165 threshold may be

adjusted.

SCK

Setting the V

TRIP

Voltage

This procedure sets the V

TRIP

to a higher voltage value. For

example, if the current V

TRIP

is 4.4V and the new V

TRIP

4.6V, this procedure directly makes the change. If the new

setting is lower than the current setting, then it is necessary

to reset the trip point before setting the new value.

FIGURE 2. RESET V

TRIP

VOLTAGE

FN8128.1

May 16, 2005

X5163, X5165

TRIP

PROGRAMMING

EXECUTE

RESET V

TRIP

SEQUENCE

SET V

= V

APPLIED =

DESIRED V

TRIP

NEW V

APPLIED =

OLD V

APPLIED + ERROR

EXECUTE

SET V

TRIP

SEQUENCE

NEW V

APPLIED =

OLD V

APPLIED - ERROR

APPLY 5V TO V

EXECUTE

RESET V

TRIP

SEQUENCE

DECREMENT V

= V

- 50MV)

RESET PIN

GOES ACTIVE?

YES

ERROR > -EMAX

MEASURED V

TRIP

–

DESIRED V

TRIP

ERROR > EMAX

ERROR < EMAX

EMAX = MAXIMUM DESIRED ERROR

DONE

FIGURE 3. V

TRIP

PROGRAMMING SEQUENCE FLOW CHART

4.7K

X5163, X5165

TRIP

ADJ.

PROGRAM

4.7K

RESET

10K

RESET V

TRIP

TEST V

TRIP

SET V

TRIP

FIGURE 4. SAMPLE V

TRIP

RESET CIRCUIT

FN8128.1

May 16, 2005

X5163, X5165

SPI Serial Memory

The memory portion of the device is a CMOS Serial EEPROM

array with Intersil’s block lock protection. The array is

internally organized as x 8. The device features a Serial

Peripheral Interface (SPI) and software protocol allowing

operation on a simple four-wire bus.

The device utilizes Intersil’s proprietary Direct Write

™

cell,

providing a minimum endurance of 100,000 cycles and a

minimum data retention of 100 years.

The device is designed to interface directly with the

synchronous Serial Peripheral Interface (SPI) of many

popular microcontroller families. It contains an 8-bit

instruction register that is accessed via the SI input, with

data being clocked in on the rising edge of SCK. CS must be

LOW during the entire operation.

All instructions (Table 1), addresses and data are transferred

MSB first. Data input on the SI line is latched on the first

rising edge of SCK after CS goes LOW. Data is output on the

SO line by the falling edge of SCK. SCK is static, allowing

the user to stop the clock and then start it again to resume

operations where left off.

Write Enable Latch

The device contains a Write Enable Latch. This latch must

be SET before a Write Operation is initiated. The WREN

instruction will set the latch and the WRDI instruction will

reset the latch (Figure 7). This latch is automatically reset

upon a power-up condition and after the completion of a

valid Write Cycle.

Status Register

The RDSR instruction provides access to the Status

during a Write Cycle. The Status Register is formatted as

follows:

WPEN

FLB

WD1

WD0

BL1

BL0

WEL

WIP

The Write-In-Progress (WIP) bit is a volatile, read only bit

and indicates whether the device is busy with an internal

nonvolatile write operation. The WIP bit is read using the

RDSR instruction. When set to a “1”, a nonvolatile write

operation is in progress. When set to a “0”, no write is in

progress.

TABLE 1. INSTRUCTION SET

INSTRUCTION NAME

WREN

SFLB

WRDI/RFLB

RSDR

WRSR

READ

WRITE

INSTRUCTION FORMAT*

0000 0110

0000 0000

0000 0100

0000 0101

0000 0001

0000 0011

0000 0010

OPERATION

Set the Write Enable Latch (Enable Write Operations)

Set Flag Bit

Reset the Write Enable Latch/Reset Flag Bit

Read Status Register

Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)

Read Data from Memory Array Beginning at Selected Address

Write Data to Memory Array Beginning at Selected Address

NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

TABLE 2. BLOCK PROTECT MATRIX

WREN CMD

WEL

STATUS REGISTER

WPEN

DEVICE PIN

WP#

BLOCK

PROTECTED BLOCK

Protected

BLOCK

UNPROTECTED BLOCK

Protected

Writable

STATUS REGISTER

WPEN, BL0, BL1, WD0,

WD1

Protected

Writable

FN8128.1

May 16, 2005

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X51638S8 Related Products

	X51638S8	X5163S8I-2.7AT1
Description	1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, PLASTIC, SOIC-8	IC,SERIAL EEPROM,2KX8,CMOS,SOP,8PIN,PLASTIC
Is it Rohs certified?	incompatible	incompatible
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation
package instruction	PLASTIC, SOIC-8	SOP, SOP8,.25
Reach Compliance Code	not_compliant	not_compliant
JESD-30 code	R-PDSO-G8	R-PDSO-G8
Number of terminals	8	8
Maximum operating temperature	70 °C	85 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE
Certification status	Not Qualified	Not Qualified
surface mount	YES	YES
Temperature level	COMMERCIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING
Terminal location	DUAL	DUAL

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