Preliminary Information
X5563
CPU Supervisor with 256Kbit SPI EEPROM
FEATURES
• Low V
CC
detection and reset assertion
—Four standard reset threshold voltages
—Re-program low V
CC
reset threshold voltage
using special programming sequence
—Reset signal valid to V
CC
= 1V
• Selectable POR time (150ms or 800ms)
• Selectable watchdog time
—(0.15s, 0.4s, 0.8s, off)
• Debounced Manual Reset Input
• Low power consumption
—<90µA max standby current, watchdog on
—<50µA max standby current, watchdog off
—<1.5mA max active current during read
• 256Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
programmable Block Lock
™
protection
—In circuit programmable ROM mode
• 10MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V power supply operation
• Available packages
—8-lead SOIC
DESCRIPTION
These devices combines power-on reset control,
watchdog timer, supply voltage supervision, manual
reset, block lock protect and serial EEPROM in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET active for a selected
period of time. This allows the power supply and oscil-
lator to stabilize before the processor can execute
code.
BLOCK DIAGRAM
Watchdog Transition
Detector
WP
SO
SI
Data
Register
Protect Logic
Status
Register
EEPROM Array
Reset &
Watchdog
Timebase
Watchdog
Timer Reset
X-Decoder
SCK
CS
Command
Decode, Test &
Control
Logic
512 X 512
RESET/MR
V
CC
V
CC
Monitor
Logic
+
V
TRIP
-
Power on,
Low Voltage
Reset
Generation
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Characteristics subject to change without notice.
1 of 18
X5563 – Preliminary Information
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the RESET signal. The
user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The device’s low V
CC
detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when V
CC
falls below the minimum V
CC
trip
point (V
TRIP
). RESET is asserted until V
CC
returns to
proper operating level and stabilizes. Xicor’s unique cir-
cuits allow the threshold for either voltage monitor to
be reprogrammed to meet special needs or to fine-tune
the threshold for applications requiring higher preci-
sion.
Ordering Information
Part Number
X5563S8-4.5A
X5563S8I-4.5A
X5563S8
X5563S8I
X5563S8-2.7A
X5563S8I-2.7A
X5563S8-2.7
X5563S8I-2.7
2.63
2.93
4.38
Vtrip1
4.63
Temperature Range
0°C–70°C
-40°C–85°C
0°C–70°C
-40°C–85°C
0°C–70°C
-40°C–85°C
0°C–70°C
-40°C–85°C
PIN CONFIGURATION
8-Pin SOIC
CS/WDI
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
CC
RESET/MR
SCK
SI
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Characteristics subject to change without notice.
2 of 18
X5563 – Preliminary Information
PIN DEFINITIONS
Pin
1
Name
CS/WDI
Function
Chip Select Input.
CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any opera-
tion after power up, a HIGH to LOW transition on CS is required.
Watchdog Input.
A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in RESET going
active.
Serial Output.
SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
Write Protect.
The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits.
Ground
Serial Input.
SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on
this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output. The rising
edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of
SCK changes the data output on the SO pin.
Output/Manual Reset Input
. This is an Input/Output pin.
RESET Output
. This is an active LOW, open drain output which goes active whenever V
CC
falls
below the minimum V
CC
sense level. When RESET is active communication to the device is inter-
rupted. RESET remains active until V
CC
rises above the minimum V
CC
sense level for 150ms.
RESET also goes active on power up and remains active for 150ms after the power supply
stabilizes.
MR Input
. This is an active LOW debounced input. When MR is active, the RESET pin is asserted.
When MR is released, RESET remains asserted for t
PURST
, and is then released.
Supply Voltage
2
3
4
5
SO
WP
V
SS
SI
6
SCK
7
RESET/MR
8
V
CC
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Characteristics subject to change without notice.
3 of 18
X5563 – Preliminary Information
PRINCIPLES OF OPERATION
Power on Reset
Application of power to the X5563 activates a Power
On Reset Circuit. This circuit goes active at about 1V
and pulls the RESET pin active. This signal prevents the
system microprocessor from starting to operate with
insufficient voltage or prior to stabilization of the oscilla-
tor. When V
CC
exceeds the device V
TRIP
value for
150ms (nominal) the circuit releases RESET, allowing
the processor to begin executing code.
Low V
CC
Voltage Monitoring
During operation, the X5563 monitors the V
CC
level
and asserts RESET if supply voltage falls below a pre-
set minimum V
TRIP
. During this time the communica-
tion to the device is interrupted. The RESET signal
also prevents the microprocessor from operating in a
power fail or brownout condition. The RESET signal
remains active until the voltage drops below 1V. The
signal remains active until V
CC
returns and exceeds
V
TRIP
for t
PURST
.
Manual Reset
By connecting a push-button from MR to ground or
driven by logic, the designer adds manual system reset
capability. The MR/RESET pin is asserted when the
push-button is closed and remain asserted for t
PURST
after the push-button is released. This pin is
debounced so a push-button connected directly to the
device will have both clean falling and rising edges on
MR.
Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the CS pin. The microproces-
sor must toggle the CS pin HIGH to LOW periodically
prior to the expiration of the watchdog time out period
to prevent a RESET signal. The state of two nonvolatile
control bits in the Status Register determines the
watchdog timer period. The microprocessor can
change these watchdog bits by writing to the status
register.
V
CC
Threshold Reset Procedure
The X5563 is shipped with standard V
CC
threshold
(V
TRIP
) voltages. These values will not change over
normal operating and storage conditions. However, in
applications where the standard thresholds are not
exactly right, or if higher precision is needed in the
threshold value, the X5563 trip points may be adjusted.
The procedure is described below, and uses the appli-
cation of a high voltage control signal.
Setting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a higher or
lower voltage value. It is necessary to reset the trip
point before setting the new value to a lower level.
To set the new voltage, apply the desired V
TRIP
thresh-
old voltage to the V
CC
pin, then tie the WP pin to the
programming voltage V
P
. Then, send the WREN com-
mand and write to address 01h to program V
TRIP
, (fol-
lowed by data byte 00h). The CS going high after a
valid write operating initiates the programming
sequence. Bring WP LOW to complete the operation.
Note:
This operation will not alter the contents of the
EEPROM.
C
ASE
A
If the V
TRIPX
(actual) is lower than the V
TRIPX
(desired), then add the difference between V
TRIPX
(desired) and V
TRIPX
(actual) to the original V
TRIPX
(desired). This is your new V
TRIPX
voltage that should
be applied to VXMON and the whole sequence
repeated again (see Fig 6).
C
ASE
B
If the V
TRIPX
(actual) is higher than the V
TRIPX
(desired), perform the reset sequence as described in
the next section. The new V
TRIPX
voltage to be applied
to VXMON will now be: V
TRIPX
(desired) – (V
TRIPX
(desired) – V
TRIPX
(actual)).
Resetting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a “native”
voltage level. For example, if the current V
TRIP
is 4.4V
and the new V
TRIP
must be 4.0V, then the V
TRIP
must
be reset. When the threshold is reset, the new level is
something less than 1.7V. This procedure must be
used to set the voltage to a lower value.
To reset the new V
TRIP
, apply greater than 3V to V
CC
and tie the WP pin to the programming voltage V
P
.
Then send the WREN command and write to address
0Bh to reset the V
TRIP
(followed by data byte 00h). The
CS going LOW to HIGH after a valid write operation ini-
tiates the programming sequence. Bring WP LOW to
complete the operation.
Note:
This operation does not change the contents of
the EEPROM array.
Characteristics subject to change without notice.
REV 1.8 9/30/02
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4 of 18
X5563 – Preliminary Information
Figure 1. Set V
TRIP
Level Sequence (V
CC
= desired V
TRIP
)
WP
V
P
= 10-15V
CS
0 1 2 3 4 5 6 7
SCK
16 Bits
SI
06h
WREN
02h
Write
0001h
Address
Addr 01h: Set V
CC
trip
00h
Data
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23
Figure 2. Reset V
TRIP
Level Sequence (V
CC
> 3V. WP = 10-15V)
WP
V
P
= 10-15V
CS
0 1 2 3 4 5 6 7
SCK
16 Bits
SI
06h
WREN
02h
Write
0003h
Address
Addr 03h: Update V
CC
trip
00h
Data
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23
Figure 3. Sample V
TRIP
Reset Circuit
4.6K
V
P
Adjust
V
TRIP
Adj.
X5563
CS
SO
WP
V
SS
V
CC
RESET
SCK
SI
RESET
SCK
SI
SO
CS
µC
Run
REV 1.8 9/30/02
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Characteristics subject to change without notice.
5 of 18
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