4K
X4043/45
CPU Supervisor with 4Kbit EEPROM
512 x 8 Bit
FEATURES
• Selectable watchdog timer
• Low V
CC
detection and reset assertion
—Five standard reset threshold voltages
—Adjust low V
CC
reset threshold voltage using
special programming sequence
—Reset signal valid to V
CC
= 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 4Kbits of EEPROM
—16-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes
of EEPROM array with Block Lock
™
protection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8-lead SOIC
—8-lead MSOP
—8-lead PDIP
DESCRIPTION
The X4043/45 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply
Voltage Supervision, and Block Lock Protect Serial
EEPROM Memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcon-
troller fails to restart a timer within a selectable time
out interval, the device activates the RESET/RESET
signal. The user selects the interval from three preset
values. Once selected, the interval does not change,
even after cycling the power.
The device’s low V
CC
detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when V
CC
falls below the minimum V
CC
trip
point. RESET/RESET is asserted until V
CC
returns to
proper operating level and stabilizes. Five industry stan-
dard V
TRIP
thresholds are available, however, Xicor’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
BLOCK DIAGRAM
Watchdog Transition
Detector
WP
SDA
Data
Register
Command
Decode &
Control
Logic
V
CC
Threshold
Reset logic
Block Lock Control
Protect Logic
Status
Register
EEPROM Array
2Kbits 1Kb 1Kb
RESET (X4043)
RESET (X4045)
Reset &
Watchdog
Timebase
Watchdog
Timer Reset
SCL
V
CC
V
TRIP
+
-
Power on and
Low Voltage
Reset
Generation
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X4043/45
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
an 2-wire interface and software protocol allowing
operation on an I
2
C bus.
The device utilizes Xicor’s proprietary Direct Write
™
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
8-Pin JEDEC SOIC, MSOP, PDIP
NC
NC
RESET
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
Pin
(SOIC/MSOP/DIP)
1
2
3
Name
NC
NC
RESET/
RESET
No internal connections
No internal connections
Function
Reset Output
. RESET is an active LOW, open drain output which goes active
whenever V
CC
falls below V
TRIP
. It will remain active until V
CC
rises above the V
TRIP
for t
PURST
. RESET/RESET goes active if the Watchdog Timer is enabled and SDA
remains either HIGH or LOW longer than the selectable Watchdog time out period.
RESET/RESET goes active on power up and remains active for 250ms after the
power supply stabilizes. RESET is an active high open drain output. An external pull
up resistor is required on the RESET/RESET pin.
Ground
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or
open collector outputs. This pin requires a pull up resistor and the input buffer is
always active (not gated).
Serial Clock.
The Serial Clock input controls the serial bus timing for data input and
output.
Write Protect.
WP HIGH prevents writes to any location in the device (including the
control register). Connect WP pin to V
SS
when it is not used.
Supply Voltage
4
5
V
SS
SDA
6
7
8
SCL
WP
V
CC
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X4043/45
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X4043/45 activates a Power
On Reset Circuit that pulls the RESET/RESET pin
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
When V
CC
exceeds the device V
TRIP
threshold value
for 200ms (nominal) the circuit releases RESET/
RESET allowing the system to begin operation.
Low Voltage Monitoring
During operation, the X4043/45 monitors the V
CC
level
and asserts RESET/RESET if supply voltage falls
below a preset minimum V
TRIP
. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V
CC
returns and exceeds
V
TRIP
for 200ms.
Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
(RESET/RESET) signal going active. A minimum
sequence to reset the watchdog timer requires four
microprocessor intructions namely, a Start, Clock Low,
Clock High and Stop. (See Page 18) The state of two
nonvolatile control bits in the status register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked”
by tying the WP pin HIGH.
Figure 1. Watchdog Restart
.6µs
SCL
1.3µs
SDA
Start
WDT Reset
Stop
EEPROM Inadvertent Write Protection
When RESET/RESET goes active as a result of a low
voltage condition (V
CC
< V
TRIP
), any in-progress com-
munications are terminated. While V
CC
< V
TRIP
, no
new communications are allowed and no nonvolatile
write operation can start. Nonvolatile writes in-progress
when RESET/RESET goes active are allowed to finish.
Additional protection mechanisms are provided with
memory block lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
TRIP
Programming
The X4043/45 is shipped with a standard V
CC
thresh-
old (V
TRIP
) voltage. This value will not change over
normal operating and storage conditions. However, in
applications where the standard V
TRIP
is not exactly
right, or if higher precision is needed in the V
TRIP
value, the X4043/45 threshold may be adjusted. The
procedure is described below, and uses the application
of a high voltage control signal.
Figure 2. Set V
TRIP
Level Sequence (V
CC
= desired V
TRIP
values WEL bit set)
WP
V
P
= 15-18V
0 1 2 3 4 5 6 7
SCL
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SDA
A0h
01h
00h
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X4043/45
Setting a V
TRIP
Voltage
There are two procedures used to set the threshold
voltages (V
TRIP
), depending if the threshold voltage to
be stored is higher or lower than the present value. For
example, if the present V
TRIP
is 2.9 V and the new
V
TRIP
is 3.2 V, the new voltage can be stored directly
into the V
TRIP
cell. If however, the new setting is to be
lower than the present setting, then it is necessary to
“reset” the V
TRIP
voltage before setting the new value.
Setting a Higher V
TRIP
Voltage
To set a V
TRIP
threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired V
TRIP
threshold voltage to the V
CC
. Then, a
programming voltage (Vp) must be applied to the WP
pin before a START condition is set up on SDA. Next,
issue on the SDA pin the Slave Address A0h, followed
by the Byte Address 01h for V
TRIP
and a 00h Data
Byte in order to program V
TRIP
. The STOP bit following
a valid write operation initiates the programming
sequence. WP pin must then be brought LOW to com-
plete the operation.
To check if the V
TRIP
has been set, first power down
the device. Slowly ramp up V
CC
and observe when the
output, RESET (4043) or RESET (4045) switches. The
voltage at which this occurs is the V
TRIP
(actual) (see
Figure 2).
C
ASE
A
Now if the desired V
TRIP
is greater than the V
TRIP
(actual), then add the difference between V
TRIP
(desired) – V
TRIP
(actual) to the original V
TRIP
desired.
This is your new V
TRIP
that should be applied to V
CC
and the whole sequence should be repeated again
(see Figure 5).
C
ASE
B
Now if the V
TRIP
(actual), is higher than the V
TRIP
(desired), perform the reset sequence as described in
the next section. The new V
TRIP
voltage to be applied
to V
CC
will now be: V
TRIP
(desired) – (V
TRIP
(actual) –
V
TRIP
(desired)).
Note:
This operation does not corrupt the memory
array.
Setting a Lower V
TRIP
Voltage
In order to set V
TRIP
to a lower voltage than the
present value, then V
TRIP
must first be “reset” accord-
ing to the procedure described below. Once V
TRIP
has
been “reset”, then V
TRIP
can be set to the desired volt-
age using the procedure described in “Setting a Higher
V
TRIP
Voltage”.
Resetting the V
TRIP
Voltage
To reset a V
TRIP
voltage, apply the programming volt-
age (Vp) to the WP pin before a START condition is set
up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h fol-
lowed by 00h for the Data Byte in order to reset V
TRIP
.
The STOP bit following a valid write operation initiates
the programming sequence. Pin WP must then be
brought LOW to complete the operation.
After being reset, the value of V
TRIP
becomes a nomi-
nal value of 1.7V or lesser.
Note:
This operation does not corrupt the memory
array.
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X4043/45
Figure 3. Reset V
TRIP
Level Sequence (V
CC
> 3V. WP = 15–18V, WEL bit set)
WP
V
P
= 15-18V
0 1 2 3 4 5 6 7
SCL
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SDA
A0h
03h
00h
Figure 4. Sample V
TRIP
Reset Circuit
V
P
4.7K
RESET
V
TRIP
Adj.
1
2
3
X4043
4
8
7
6
5
Run
SCL
SDA
Adjust
µC
REV 1.1.17 9/14/01
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Characteristics subject to change without notice.
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