DAC 3550A
Contents
Page
3
3
5
5
6
6
6
6
6
6
7
7
8
8
8
9
9
9
9
10
10
10
12
12
12
12
13
13
14
15
17
17
18
20
25
25
25
26
26
27
27
27
28
32
Section
1.
1.1.
2.
2.1.
2.2.
2.3.
2.4.
2.5.
2.6.
2.7.
2.8.
2.9.
2.10.
2.10.1.
2.10.2.
2.11.
2.12.
2.13.
2.14.
3.
3.1.
3.2.
3.3.
3.3.1.
3.3.2.
3.3.3.
3.3.4.
3.4.
3.5.
3.6.
3.7.
3.7.1.
3.7.2.
3.7.3.
4.
4.1.
4.2.
4.3.
4.4.
4.5.
4.5.1.
4.5.2.
4.6.
5.
Title
Introduction
Main Features
Functional Description
I
2
S Interface
Interpolation Filter
Variable Sample and Hold
3rd-order Noise Shaper and Multibit DAC
Analog Low-pass
Input Select and Mixing Matrix
Postfilter Op Amps, Deemphasis Op Amps, and Line-Out
Analog Volume
Headphone Amplifier
Clock System
Standard Mode
MPEG Mode
I
2
C Bus Interface
Registers
Chip Select
Reduced Feature Mode
Specifications
Outline Dimensions
Pin Connections and Short Descriptions
Pin Descriptions
Power Supply Pins
Analog Audio Pins
Oscillator and Clock Pins
Other Pins
Pin Configuration
Pin Circuits
Control Registers
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Characteristics
Applications
Line Output Details
Recommended Low-Pass Filters for Analog Outputs
Recommendations for Filters and Deemphasis
Recommendations for MegaBass Filter without Deemphasis plus 1st-order low-pass
Power-up/down Sequence
Power-up Sequence
Power-down Sequence
Typical Applications
Data Sheet History
2
Micronas
DAC 3550A
Stereo Audio DAC
1. Introduction
The DAC 3550A is a single-chip, high-precision, dual
digital-to-analog converter designed for audio applica-
tions. The employed conversion technique is based on
oversampling with noise-shaping.
With Micronas’ unique multibit sigma-delta technique,
less sensitivity to clock jitter, high linearity, and a supe-
rior S/N ratio has been achieved. The DAC 3550A is
controlled via I
2
C bus.
Digital audio input data is received by a versatile I
2
S
interface. The analog back-end consists of internal
analog filters and op amps for cost-effective additional
external sound processing. The DAC 3550A provides
line-out, headphone/speaker amplifiers, and volume
control. Moreover, mixing additional analog audio
sources to the D/A-converted signal is supported.
The DAC 3550A is designed for all kinds of applica-
tions in the audio and multimedia field, such as:
MPEG players, CD players, DVD players, CD-ROM
players, etc. The DAC 3550A ideally complements the
MPEG 1/2 layer 2/3 audio decoder MAS 3507D.
No crystal required for standard applications with
sample rates from 32 to 48 kHz.
Crystal required
only for automatic sample rate detection below 32 kHz,
MPEG mode (refer to Section 2.10), and use of clock
output CLKOUT.
1.1. Main Features
– no master main input clock required
– integrated stereo headphone amplifier and mono
speaker amplifier
– SNR of 103 dBA
– I
2
C bus, I
2
S bus
– internal clock oscillator
– full-feature mode by I
2
C control (three selectable
subaddresses)
– reduced feature mode for non-I
2
C applications
– continuous sample rates from 8 kHz to 50 kHz
– analog deemphasis for 44.1 kHz
– analog volume and balance: +18…
−
75 dB and mute
– oversampling and multibit noise-shaping technique
– THD better than 0.01 %
– two additional analog stereo inputs (AUX) with
source selection and mixing
– supply range: 2.7 V…5.5 V
– low-power mode
– additional line-out
– on-chip op amps for cost-effective external analog
sound processing
Analog Inputs
WSI
CLI
DRI
I
2
S
Inter-
polation
Filter
DAC
Input
Select
and
Mixing
Volume
and
Headphone
Amplifier
OUTL
OUTR
Fig. 1–1:
Block diagram of the DAC 3550A
demand signal
Host
(PC, Controller)
MPEG clock
MPEG bit stream
MAS
3507D
I
2
S
DAC
3550A
line out
14.725 MHz
ROM, CD-ROM,
RAM, Flash Mem. ..
CLKOUT
Fig. 1–2:
Typical application: MPEG Layer 3 Player
Micronas
3
DAC 3550A
2. Functional Description
2.1. I
2
S Interface
The I
2
S interface is the digital audio interface between
the DAC 3550A and external digital audio sources
such as CD/DAT players, MPEG decoders etc. It cov-
ers most of the I
2
S-compatible formats.
All modes have two common features:
1. The MSB is left justified to an I
2
S frame identifica-
tion (WSI) transition.
2. Data is valid on the rising edge of the bit clock CLI.
16-bit mode
In this case, the bit clock is 32
×
fs
audio
. Maximum word
length is 16 bit.
32-bit mode
In this case, the bit clock is 64
×
fs
audio
. Maximum word
length is 32 bit.
Left-Right Selection
Standard I
2
S format defines an audio frame always
starting with left channel and low-state of WSI. How-
ever, I
2
C control allows changing the polarity of WSI.
Delay Bit
Standard I
2
S format requires a delay of one clock
cycle between transitions of WSI and data MSB. In
order to fit other formats, however, this characteristic
can be switched off and on by I
2
C control.
Automatic Detection
No I
2
C control is required to switch between 16- and
32-bit mode. It is recommended to switch the
DAC 3550A into mute position during changing
between 16- and 32-bit mode.
For high-quality audio, it is recommended to use the
32-bit mode of the I
2
S interface to make use of the full
dynamic range (if more than 16 bits are available).
V
h
CLI
V
l
V
h
DAI
15 14 13 12 11 10 9 8
V
l
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
programmable delay bit
WSI
V
h
V
l
left 16-bit audio sample
right 16-bit audio sample
Fig. 2–1:
I
2
S 16-bit mode (LR_SEL=0)
V
h
CLI
V
l
V
h
DAI
31 30 29 28 27 26 25 24
V
l
7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 7 6 5 4 3 2 1 0
programmable delay bit
WSI
V
h
V
l
left 32-bit audio sample
right 32-bit audio sample
Fig. 2–2:
I
2
S 32-bit mode (LR_SEL=0)
Note:
Volume mute should be applied before changing
I
2
S mode in order to avoid audible clicks.
Micronas
5
Embedded System
京公网安备 11010802033920号
EEWORLD
