DMA 2275, DMA 2286
The DMA 2275 and DMA 2286 C/D/D2–MAC De-
scrambler
1. Introduction
1.1. General Information
The DMA 2275 is a digital real–time descrambling pro-
cessor for the D2–MAC/Packet system. Together with
the D2–MAC/Packet decoder chip DMA 2271, it can be
used to build up a D2–MAC/Packet conditional access
receiver.
The DMA 2286 is a digital real–time descrambling pro-
cessor for the C/D/D2–MAC/Packet system. Together
with the C/D/D2–MAC/Packet decoder chip DMA 2281,
it can be used to build up a C/D/D2–MAC/Packet condi-
tional access receiver.
The programmable VLSI circuits in CMOS technology
are housed in 68–pin packages and contain on a single
silicon chip the following functions:
DMA 2275 and DMA 2286
– descrambling of MAC video signal
– interpolation of MAC video signal (aspect ratio 16:9)
– descrambling of MAC data packets
– descrambling of VBI–teletext
– entitlement packet acquisition
– supplementary general purpose packet acquisition
DRAM
DRAM
DRAM
CASS
CCU 3000
NVM 3060
ceivers provide descrambling facility for one video ser-
vice and up to four audio or data services including
VBI–teletext. It is important to notice that the DMA 2275
or DMA 2286 do not include any decryption or security
functions. These functions will be carried out by one or
more conditional access subsystems (CASS) which
communicate with the descrambler chip via the central
control unit (CCU) and the IM bus.
CASS
CCU 3000
NVM 3060
DRAM
DRAM
D2MAC
Baseband
Signal
VCU 2133
A/D Part
DMA 2275
DMA 2271
VCU 2133
D/A Part
R
G
B
MCU 2600
TPU 2735
DRAM
AMU 2481
S1
S2
S3
S4
Fig. 1–1:
Block diagram for a stand–alone D2–MAC
decoder
– line 625 acquisition
– communication with external microprocessor via the
IM bus
DMA 2286 only
– one subframe sound processing C/D/D2–MAC
DRAM
D/D2MAC
Baseband
Signal
VCU 2133
A/D Part
DMA 2286
DMA 2281
VCU 2133
D/A Part
R
G
B
MCU 2600
TPU 2740
1.2. Environment
AMU 2481
Figures 1–1 and 1–2 show how the descrambler chips
DMA 2275 and DMA 2286 can be implemented into a
MAC conditional access receiver together with other cir-
cuits of ITT’s DIGIT 2000 digital TV system. These re-
S1
S2
S3
S4
Fig. 1–2:
Block diagram for a stand–alone D/D2–
MAC decoder
4
DMA 2275, DMA 2286
2. Chip Architecture
Figure 2–1 shows the architecture of the descrambling
chip DMA 2286. The DMA 2275 architecture is identical
to the that of the DMA 2286, except that the sound pro-
cessor is missing. The chips can be subdivided into sev-
eral functional blocks.
DMA 2275 and DMA 2286:
Video Processor
– descrambling, panning and interpolation of the video
signal
PRBS Generator
– delivers cut points and cipher streams
Sound Processor
Line 625 Processor
– acquisition of service identification data and real time
control information
– spectrum descrambling of data burst, packet deinter-
leaving (one subframe only), sound packet processing
(one subframe only)
Packet Processor
– acquisition of entitlement packets, acquisition of gen-
eral purpose packets, selection of cipher stream, des-
crambling of data packets
Interface Processor
– management of internal and external data transfer
Timing Generator
– delivers internal chip timing
DMA 2286 only:
8
Baseband
8
Video Processor
Clamping +
Video Gate
8
Baseband
Code
Converter
8
Video
Descrambler
8
Interpolation
Filter
8
Video
PRBS
Generator
PRBS Generator
Packet
PRBS
Generator
VBI
Data
Interface Processor
Timing
Generator
Fast
Processor
Packet Processor
Corrected
Packet
Data
Descrambl.
Packet
Data
Packet
Acquisition
Packet
Descrambler
Vdd
Vdd
GND
GND
Packet
Data
Burst
Data
DRAM
Interface
8
Addr.
R/W
Data
RAS
CAS
IM Bus
Interface
3
IM Bus
Timing
Generator
Line 625
Acquisition
Spectr. Descr.
Deinterleaver
Sound
Processing
12
2
Line 625 Proc.
Busy
Reset
Burst
Sync
ΦM
Sound
Proc.
DRAM
S Bus
Fig. 2–1:
Block diagram of the DMA 2286
Audio
Clock
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