FemtoClocks™ Crystal-to-3.3V LVPECL
Frequency Synthesizer
843003
DATA SHEET
General Description
The 843003 is a 3 differential output LVPECL Synthesizer
designed to generate Ethernet refer- ence clock frequencies.
Using a 31.25MHz or 26.041666MHz, 18pF parallel resonant
crystal, the following frequencies can be generated based on the
settings of 4 fre- quency select pins (DIV_SEL[A1:A0],
DIV_SEL[B1:B0]): 625MHz, 312.5MHz, 156.25MHz, and
125MHz. The 843003 has 2 output banks, Bank A with 1
differential LVPECL output pair and Bank B with 2 differential
LVPECL output pairs.
The two banks have their own dedicated frequency select pins and
can be independently set for the frequencies mentioned above.
The 843003 uses IDT’s 3
rd
generation low phase noise VCO
technology and can achieve 1ps or lower typical rms phase jitter,
easily meeting Ethernet jitter requirements. The 843003 is
packaged in a small 24-pin TSSOP package.
Features
•
•
•
•
•
Three 3.3V LVPECL outputs on two banks, A Bank with one
LVPECL pair and B Bank with 2 LVPECL output pairs
Using a 31.25MHz or 26.041666 crystal, the two output banks
can be independently set for 625MHz, 312.5MHz, 156.25MHz
or 125MHz
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
VCO range: 560MHz – 700MHz
RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.51ps (typical)
Offset
Noise Power
100Hz ................ -96.8 dBc/Hz
1kHz .................. -119.1 dBc/Hz
10kHz ................ -126.4 dBc/Hz
100kHz .............. -127.0 dBc/Hz
Pin Assignment
DIV_SELB0
VCO_SEL
MR
V
CCO_A
QA0
nQA0
OEB
OEA
FB_DIV
V
CCA
V
CC
DIV_SELA0
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DIV_SELB1
V
CCO_B
QB0
nQB0
QB1
nQB1
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
V
EE
DIV_SELA1
•
•
•
•
Full 3.3V supply mode
0°C to 70°C ambient operating temperature
Industrial temperature available upon request
Available in ead-free (RoHS 6) package
843003
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm
package body
G Package
Block Diagram
OEA
Pullup
DIV_SELA[1:0]
Pulldown:Pullup
VCO_SEL
Pullup
TEST_CLK
Pulldown
00
01
10
11
÷1
÷2
(default)
÷4
÷5
2
QA0
0
nQA0
0
XTAL_IN
OSC
XTAL_OUT
XTAL_SEL
Pullup
1
Phase
Detector
VCO
625MHz
1
QB0
FB_DIV
0 = ÷20 (default)
1 = ÷24
00
01
10
11
÷1
÷2
÷4
(default)
÷5
nQB0
QB1
nQB1
FB_DIV
Pulldown
DIV_SELB[1:0]
Pullup:Pulldown
MR
Pulldown
OEB
Pullup
2
843003 Rev A 4/7/15
1
©2015 Integrated Device Technology, Inc.
843003 DATA SHEET
Table 1. Pin Descriptions
Number
1
Name
DIV_SELB0
Input
Type
Pulldown
Description
Division select pin for Bank B. Default = Low. LVCMOS/LVTTL interface levels.
VCO select pin. When Low, the PLL is bypassed and the crystal reference or
TEST_CLK (depending on XTAL_SEL setting) are passed directly to the output
dividers. Has an internal pullup resistor so the PLL is not bypassed by default.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled. Has an internal
pulldown resistor so the power-up default state of outputs and dividers are enabled.
LVCMOS/LVTTL interface levels.
Output supply pin for Bank A outputs.
Differential output pair. LVPECL interface levels.
Output enable Bank B. Active High output enable. When logic HIGH, the output pair
on Bank B is enabled. When logic LOW, the output pair drives differential Low
(QB0 = Low, nQB0 = High). Has an internal pullup resistor so the default power-up
state of outputs are enabled. LVCMOS/LVTTL interface levels.
Output enable Bank A. Active High output enable. When logic HIGH, the 2 output
pairs on Bank A are enabled. When logic LOW, the output pair drives differential
Low (QA0 = Low, nQA0 = High). Has an internal pullup resistor so the default
power-up state of outputs are enabled. LVCMOS/LVTTL interface levels.
Feedback divide select. When Low (default), the feedback divider is set for ÷20.
When HIGH, the feedback divider is set for ÷24. LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Pullup
Pulldown
Division select pin for Bank A. Default = HIGH. LVCMOS/LVTTL interface levels.
Division select pin for Bank A. Default = Low. LVCMOS/LVTTL interface levels.
Negative supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
XTAL_IN is also the overdrive pin if you want to overdrive the crystal circuit with a
single-ended reference clock.
Pulldown
Single-ended reference clock input. Has an internal pulldown resistor to pull to low
state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the single-ended TEST_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected by
default. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pin for Bank B outputs.
Pullup
Division select pin for Bank B. Default = High. LVCMOS/LVTTL interface levels.
2
VCO_SEL
Input
Pullup
3
MR
Input
Pulldown
4
5, 6
V
CCO_A
QA0, nQA0
Power
Output
7
OEB
Input
Pullup
8
OEA
Input
Pullup
9
10
11
12
13
14
15,
16
FB_DIV
V
CCA
V
CC
DIV_SELA0
DIV_SELA1
V
EE
XTAL_OUT,
XTAL_IN
Input
Power
Power
Input
Input
Power
Input
Pulldown
17
TEST_CLK
Input
18
19, 20
21, 22
23
24
XTAL_SEL
nQB1, QB1
nQB01, QB0
V
CCO_B
DIV_SELB1
Input
Output
Output
Power
Input
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Rev A 4/7/15
2
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
843003 DATA SHEET
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Tables
Table 3A. Bank A Frequency Table
Inputs
Crystal Frequency
(MHz)
31.25
31.25
31.25
31.25
26.041666
26.041666
26.041666
26.041666
DIV_SELA1
0
0
1
1
0
0
1
1
DIV_SELA0
0
1
0
1
0
1
0
1
FB_DIV
0
0
0
0
1
1
1
1
Feedback
Divider
20
20
20
20
24
24
24
24
Bank A
Output Divider
1
2
4
5
1
2
4
5
M/N
Multiplication
Factor
20
10
5
4
24
12
6
4.8
QA0/nQA0
Output Frequency
(MHz)
625
312.5
156.25
125
625
312.5
156.25
125
Table 3B. Bank B Frequency Table
Inputs
Crystal Frequency
(MHz)
31.25
31.25
31.25
31.25
26.041666
26.041666
26.041666
26.041666
DIV_SELB1
0
0
1
1
0
0
1
1
DIV_SELB0
0
1
0
1
0
1
0
1
FB_DIV
0
0
0
0
1
1
1
1
Feedback
Divider
20
20
20
20
24
24
24
24
Bank B
Output Divider
1
2
4
5
1
2
4
5
M/N
Multiplication
Factor
20
10
5
4
24
12
6
4.8
QBx/nQBx
Output Frequency
(MHz)
625
312.5
156.25
125
625
312.5
156.25
125
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
3
Rev A 4/7/15
843003 DATA SHEET
Table 3C. Output Bank Configuration Select Function Table
Inputs
DIV_SELA1
0
0
1
1
DIV_SELA0
0
1
0
1
Bank A
Output Divider
1
2
4
5
Inputs
DIV_SELB1
0
0
1
1
DIV_SELB0
0
1
0
1
Bank B
Output Divider
1
2
4
5
Table 3D. Feedback Divider Configuration Select Function Table
Inputs
FB_DIV
0
1
Feedback Divide
20
24
Disabled
TEST_CLK
Enabled
OEA, OEB
nQA0, nQBx
QA0, QBx
Figure 1. OE Timing Diagram
Rev A 4/7/15
4
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
843003 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
70C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
V
CCA
V
CCO_A,
V
CCO_B
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
158
15
Units
V
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
IH
Parameter
Input High Voltage
DIV_SEL[A0:A1], FB_DIV,
DIV_SEL[B0:B1], OEA, OEB,
VCO_SEL, XTAL_SEL, MR
TEST_CLK
TEST_CLK, FB_DIV, MR,
DIV_SELA1, DIV_SELB0
I
IH
Input
High Current
OEA, OEB,
VCO_SEL, XTAL_SEL,
DIV_SELB1, DIV_SELA0
TEST_CLK, FB_DIV, MR,
DIV_SELA1, DIV_SELB0
I
IL
Input
Low Current
OEA, OEB,
VCO_SEL, XTAL_SEL,
DIV_SELB1, DIV_SELA0
V
CC
= V
IN
= 3.465V
Test Conditions
Minimum
2
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
1.3
150
Units
V
V
V
µA
V
IL
Input
Low Voltage
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V,
V
IN
= 0V
V
CC
= 3.465V,
V
IN
= 0V
5
µA
-5
µA
-150
µA
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
5
Rev A 4/7/15
京公网安备 11010802033920号
EEWORLD
