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FM24C256N

Description
EEPROM, 32KX8, Serial, CMOS, PDIP8, PLASTIC, DIP-8
Categorystorage    storage   
File Size86KB,12 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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FM24C256N Overview

EEPROM, 32KX8, Serial, CMOS, PDIP8, PLASTIC, DIP-8

FM24C256N Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeDIP
package instructionDIP, DIP8,.3
Contacts8
Reach Compliance Codeunknown
ECCN codeEAR99
Other features40 YEARS DATA RETENTION
Maximum clock frequency (fCLK)0.1 MHz
Data retention time - minimum40
Durability100000 Write/Erase Cycles
I2C control byte1010DDDR
JESD-30 codeR-PDIP-T8
JESD-609 codee0
length9.817 mm
memory density262144 bit
Memory IC TypeEEPROM
memory width8
Number of functions1
Number of terminals8
word count32768 words
character code32000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX8
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP8,.3
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialSERIAL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height5.08 mm
Serial bus typeI2C
Maximum standby current0.00005 A
Maximum slew rate0.001 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
Maximum write cycle time (tWC)6 ms
write protectHARDWARE
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
June 2000
FM24C256
256 KBit 2-Wire Bus Interface
Serial EEPROM with Write Protect
General Description
The FM24C256/C256L/C256LZ devices are 256 Kbits CMOS
nonvolatile electrically erasable memory. These devices offer the
designer different low voltage and low power options. They
conform to all requirements in the Extended IIC 2-wire protocol.
Furthermore, they are designed to minimize device pin count and
simplify PC board layout requirements.
The entire memory array can be write disabled (Write Protection)
by connecting the WP pin to V
CC
.
Functional address lines allow up to eight devices on the same
bus, for up to a total of 2 Mbit address space.
The IIC communication protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power con-
sumption.
Features
I
Extended Operating Voltages
— C256: 4.5V - 5.5V
— C256L: 2.7V - 5.5V
— C256LZ: 2.7V - 5.5V
I
Low Power CMOS
— 1mA active current typical
— C256/C256L: 10µA standby current typical
— C256LZ: less than 1µA standby current
I
2-wire IIC serial interface
I
64 byte page write mode
I
Max write cycle time of 6ms byte/page
I
40 years data retention
I
Endurance: 100,000 data changes
I
Hardware write protect for entire array
I
Schmitt trigger inputs for noise suppression
I
Electrostatic discharge protection > 4000V
I
8-pin DIP and 8-pin SO (150 mil) packages. Contact factory
for CSP package availability
Block Diagram
VCC
WP
SDA
START
STOP
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
LOAD
A2
A1
A0
WORD
ADDRESS
COUNTER
INC
E2PROM
ARRAY
WRITE
LOCKOUT
START CYCLE
H.V. GENERATION
TIMING &CONTROL
SCL
XDEC
R/W
YDEC
CK
DIN
DATA REGISTER
DOUT
DS800023-1
© 2000 Fairchild Semiconductor International
FM24C256 rev. B.3
1
www.fairchildsemi.com

FM24C256N Related Products

FM24C256N FM24C256M8
Description EEPROM, 32KX8, Serial, CMOS, PDIP8, PLASTIC, DIP-8 EEPROM, 32KX8, Serial, CMOS, PDSO8, PLASTIC, SOIC-8
Is it Rohs certified? incompatible incompatible
Parts packaging code DIP SOIC
package instruction DIP, DIP8,.3 SOP, SOP8,.25
Contacts 8 8
Reach Compliance Code unknown unknown
ECCN code EAR99 EAR99
Other features 40 YEARS DATA RETENTION 40 YEARS DATA RETENTION
Maximum clock frequency (fCLK) 0.1 MHz 0.1 MHz
Data retention time - minimum 40 40
Durability 100000 Write/Erase Cycles 100000 Write/Erase Cycles
I2C control byte 1010DDDR 1010DDDR
JESD-30 code R-PDIP-T8 R-PDSO-G8
JESD-609 code e0 e0
length 9.817 mm 4.9 mm
memory density 262144 bit 262144 bit
Memory IC Type EEPROM EEPROM
memory width 8 8
Number of functions 1 1
Number of terminals 8 8
word count 32768 words 32768 words
character code 32000 32000
Operating mode SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 70 °C 70 °C
organize 32KX8 32KX8
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP SOP
Encapsulate equivalent code DIP8,.3 SOP8,.25
Package shape RECTANGULAR RECTANGULAR
Package form IN-LINE SMALL OUTLINE
Parallel/Serial SERIAL SERIAL
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED
power supply 5 V 5 V
Certification status Not Qualified Not Qualified
Maximum seat height 5.08 mm 1.75 mm
Serial bus type I2C I2C
Maximum standby current 0.00005 A 0.00005 A
Maximum slew rate 0.001 mA 0.001 mA
Maximum supply voltage (Vsup) 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V
surface mount NO YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE GULL WING
Terminal pitch 2.54 mm 1.27 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
width 7.62 mm 3.9 mm
Maximum write cycle time (tWC) 6 ms 6 ms
write protect HARDWARE HARDWARE

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