UPD44165082F5-E50-EQ1 datasheet, PDF

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UPD44165082F5-E50-EQ1: DescriptionIC,SYNC SRAM,QDR,2MX8,CMOS,BGA,165PIN; Categorystorage storage; File Size308KB，32 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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UPD44165082F5-E50-EQ1 Overview

IC,SYNC SRAM,QDR,2MX8,CMOS,BGA,165PIN

UPD44165082F5-E50-EQ1 Parametric

Parameter Name	Attribute value
Maker	Renesas Electronics Corporation
Parts packaging code	BGA
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	0.38 ns
Maximum clock frequency (fCLK)	200 MHz
I/O type	SEPARATE
JESD-30 code	R-XBGA-B165
memory density	16777216 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
organize	2MX8
Output characteristics	3-STATE
encapsulated code	BGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum standby current	0.17 A
Minimum standby current	1.7 V
Maximum slew rate	0.49 mA
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM

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DATA SHEET

MOS INTEGRATED CIRCUIT

PD44165082, 44165182, 44165362

18M-BIT QDR

II SRAM

2-WORD BURST OPERATION

Description

The

PD44165082 is a 2,097,152-word by 8-bit, the

PD44165182 is a 1,048,576-word by 18-bit and the

PD44165362 is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS

technology using full CMOS six-transistor memory cell.

The

PD44165082,

PD44165182 and

PD44165362 integrate unique synchronous peripheral circuitry and a burst

counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K.

These products are suitable for application which require synchronous operation, high speed, low voltage, high

density and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

•

1.8 ± 0.1 V power supply and HSTL I/O

•

DLL circuitry for wide output data valid window and future frequency scaling

•

Separate independent read and write data ports with concurrent transactions

•

100% bus utilization DDR READ and WRITE operation

•

Two-tick burst for low DDR transaction size

•

Two input clocks (K and /K) for precise DDR timing at clock rising edges only

•

Two output clocks (C and /C) for precise flight time and clock skew matching-clock

and data delivered together to receiving device

•

Internally self-timed write control

•

Clock-stop capability with

s restart

•

User programmable impedance output

•

Fast clock cycle time : 5.0 ns (200 MHz), 6.0 ns (167 MHz), 7.5 ns (133 MHz)

•

Simple control logic for easy depth expansion

•

JTAG boundary scan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M15824EJ8V0DS00 (8th edition)

Date Published April 2007 NS CP(N)

Printed in Japan

The mark <R> shows major revised points.

2001

The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.

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