82562ET 10/100 Mbps Platform LAN
Connect (PLC)
Networking Silicon
Datasheet
Product Features
■
■
■
■
■
■
■
■
IEEE 802.3 10BASE-T/100BASE-TX
compliant physical layer interface
IEEE 802.3u Auto-Negotiation support
Digital Adaptive Equalization control
Link status interrupt capability
XOR tree mode support
3-port LED support (speed, link and
activity)
10BASE-T auto-polarity correction
LAN Connect Interface
■
■
■
■
■
■
■
Diagnostic loopback mode
1:1 transmit transformer ratio support
Low power (less than 300 mW in active
transmit mode)
Reduced power in “unplugged mode” (less
than 50 mW)
Automatic detection of “unplugged mode”
3.3 V device
48-pin Shrink Small Outline Package
Revision 1.4
November 2006
Revision History
Revision
0.55
0.6
Revision Date
Sept. 1999
Nov. 1999
Initial release.
• Corrected Figure 4 “NRZ to MLT-3 Encoding Diagram on Pg. 11 to reflect
correct signal transitions.
• Removed “10BASE-T Error Detection and Reporting” section since the
82562 does not do 10BASE-T error reporting.
• Updated bit 13 of Table 3 “Register 16 (10 Hexadecimal): PLC Status, Con-
trol and Address Data” to reflect correct values.
Advance Information Datasheet release (Intel Secret).
• Modified Table 1 “82562ET Hardware Configuration” to add one row for
XOR Tree and include column for comments.
• Updated the descrition of the Activity LED signal in Section 3.6, “LED
Pins”.
• Revised Section 3.7, “Miscellaneous Control Pins” to reflect references to
Table 1 “82562ET Hardware Configuration”.
• Updated Section 6.0, “Electrical and Timing Specifications”.
• Replaced diagrams in Section 7.1, “Package Information”.
Advance Information Datasheet release (Intel Confidential).
• On cover page, replaced Boundary Scan Support with XOR tree mode
support. Added bullet for LAN Connect I/F.
• Pg. 3, added a Solution Block Diagram as included in OR-2338 Pg. 4 but
replaced EM with ET in diagram.
• Pg. 11, removed Figure 4, “NRZ to MLT-3 Encoding Diagram”.
• Pg. 35, changed the Rev. number on the 82562 Pinout symbol to 1.0.
Removed confidential status.
• Removed sections: “Physical Layer Interface Functionality” and “Platform
LAN Connect”.
• Changed “Electrical and Timing Specifications” section to “Voltage and
Temperature Specifications” and removed timing specifications.
• Added product ordering code in Section 1.0.
• Corrected the TESTEN signal description.
Description
1.0
May 2000
1.1
June 2000
1.2
Oct 2001
1.3
1.4
March 2003
Nov 2006
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating
to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82562ET PLC may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © 2006, Intel Corporation
Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
* Other brands and names are the property of their respective owners.
Datasheet
Networking Silicon — 82562ET
Contents
1.0
Introduction......................................................................................................................... 1
1.1
1.2
1.3
1.4
2.0
3.0
Overview ............................................................................................................... 1
Features ................................................................................................................ 1
References ............................................................................................................ 1
Product Code ........................................................................................................2
82562ET Architectural Overview........................................................................................ 3
82562ET Signal Descriptions ............................................................................................. 5
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Signal Type Definitions ......................................................................................... 5
Twisted Pair Ethernet (TPE) Pins ......................................................................... 5
External Bias Pins ................................................................................................ 5
Clock Pins ............................................................................................................ 6
Platform LAN Connect Interface Pins.................................................................... 6
LED Pins ..............................................................................................................7
Miscellaneous Control Pins .................................................................................. 7
Power and Ground Connections .......................................................................... 8
100BASE-TX Mode ............................................................................................... 9
4.1.1 100BASE-TX Transmit Blocks .................................................................9
4.1.2 100BASE-TX Receive Blocks ................................................................11
10BASE-T Mode .................................................................................................12
4.2.1 10BASE-T Transmit Blocks ....................................................................12
4.2.2 10BASE-T Receive Blocks .....................................................................13
Analog References..............................................................................................14
Dynamic Reduced Power & Auto Plugging Detection.........................................14
4.4.1 Auto Plugging Detection.........................................................................14
4.4.2 Dynamic Reduced Power.......................................................................15
4.4.3 Configuration ..........................................................................................15
Reset ...................................................................................................................15
LAN Connect Interface ........................................................................................16
4.6.1 LAN Connect Clock ................................................................................16
4.6.2 LAN Connect Reset................................................................................16
LED Functionality ...............................................................................................16
Medium Dependent Interface Registers 0 through 7...........................................17
5.1.1 Register 0: Control Register Bit Definitions ...........................................17
5.1.2 Register 1: Status Register Bit Definitions ............................................18
5.1.3 Register 2: PHY Identifier Register Bit Definitions ................................19
5.1.4 Register 3: PHY Identifier Register Bit Definitions ................................19
5.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions ....20
5.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions .
20
5.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions ..........20
Medium Dependent Interface Registers 8 through 15.........................................21
4.0
Physical Layer Interface Functionality................................................................................ 9
4.1
4.2
4.3
4.4
4.5
4.6
4.7
5.0
5.1
Platform LAN Connect Registers .....................................................................................17
5.2
Datasheet
iii
82562ET — Networking Silicon
5.3
Medium Dependent Interface Registers 16 through 31 ...................................... 21
5.3.1 Register 16: PHY Status and Control Register Bit Definitions .............. 21
5.3.2 Register 17: PHY Unit Special Control Bit Definitions ........................... 22
5.3.3 Register 18: PHY Address Register ....................................................... 23
5.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions
23
5.3.5 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions ...
23
5.3.6 Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions .
23
5.3.7 Register 22: Receive Symbol Error Counter Bit Definitions .................. 24
5.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error
Counter Bit Definitions 24
5.3.9 Register 24: 10BASE-T Receive End of Frame Error Counter Bit Defini-
tions 24
5.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions ..
24
5.3.11 Register 27: PHY Unit Special Control Bit Definitions ........................... 24
Absolute Maximum Ratings ................................................................................ 27
DC Characteristics ............................................................................................. 27
6.2.1 X1 Clock DC Specifications ................................................................... 27
6.2.2 LAN Connect Interface DC Specifications ............................................. 28
6.2.3 LED DC Specifications .......................................................................... 28
6.2.4 10BASE-T Voltage and Current DC Specifications ............................... 28
6.2.5 100BASE-TX Voltage and Current DC Specifications .......................... 29
AC Characteristics .............................................................................................. 30
6.3.1 10BASE-T Normal Link Pulse (NLP) Timing Parameters ..................... 30
6.3.2 Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ................. 31
6.3.3 100BASE-TX Transmitter AC Specifications ......................................... 32
6.3.4 Reset (RSTSYNC) AC Specifications ................................................... 32
Package Information ........................................................................................... 33
Pinout Information ............................................................................................... 34
7.2.1 82562ET Pin Assignments .................................................................... 34
7.2.2 82562ET Shrink Small Outlying Package Diagram ............................... 35
6.0
Electrical and Timing Specifications................................................................................. 27
6.1
6.2
6.3
7.0
Package and Pinout Information ...................................................................................... 33
7.1
7.2
iv
Datasheet
Networking Silicon — 82562ET
1.0
1.1
Introduction
Overview
The Intel
®
82562ET is a highly-integrated Platform LAN Connect device designed for 10 or 100
Mbps Ethernet systems. It is based on the IEEE 10BASE-T and 100BASE-TX standards. The
IEEE 802.3u standard for 100BASE-TX defines networking over two pairs of Category 5
unshielded twisted pair cable or Type 1 shielded twisted pair cable.
The 82562ET complies with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full
Duplex Flow Control standard. The 82563ET also includes a PHY interface compliant to the
current platform LAN connect interface.
1.2
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface
IEEE 802.3u Auto-Negotiation support
Digital Adaptive Equalization control
Link status interrupt capability
XOR Tree mode support for board testing
3-port LED support (speed, link and activity)
10BASE-T auto-polarity correction
Diagnostic loopback mode
1:1 transmit transformer ratio support
Low power (less than 300 mW in active transmit mode)
Reduced power in “unplugged mode” (less than 50 mW)
Automatic detection of “unplugged mode”
3.3 V device
48-pin Shrink Small Outline Package
Platform LAN connect interface support
1.3
References
•
IEEE 802.3 Standard for Local and Metropolitan Area Networks, Institute of Electrical and
Electronics Engineers
•
82555 10/100 Mbps LAN Physical Layer Interface Datasheet, Intel Corporation
•
LAN Connect Interface Specification, Intel Corporation
Datasheet
1
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