PC7448
PowerPC 7448 RISC Microprocessor
Datasheet -
Preliminary Specification
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3000 Dhrystone 2.1 MIPS at 1.3 GHz
Selectable Bus Clock (30 CPU Bus Dividers up to 28x)
Selectable MPx/60x Interface Voltage (1.5V; 1,8V; 2.5V)
P
D
Typically 10W at 1.25 GHz at V
DD
= 1.1V
Full Operating Conditions
Nap, Doze and Sleep Power Saving Modes
Superscalar (Four Instructions Fetched Per Clock Cycle)
4 GB Direct Addressing Range
Virtual Memory: 4 Hexabytes (2
52
)
64-bit Data and 36-bit Address Bus Interface
Integrated L1: 32 KB Instruction and 32 KB Data Cache
Integrated L2: 1 MB with ECC
11 Independent Execution Units and 3 Register Files
Write-back and Write-through Operations
f
INT
Max = 1.25 GHz
f
BUS
Max = 133 MHz/166 MHz and 200 MHz
Description
This document is primarily concerned with the PowerPC
®
PC7448. The PC7448 is an implementation of the PowerPC
microprocessor family of Reduced Instruction Set Computer (RISC) microprocessors. This document describes pertinent
electrical and physical characteristics of the PC7448. For information regarding specific PC7448 part numbers covered by
this document and part numbers covered by other documents,
See “Ordering Information” on page 49.”
For functional char-
acteristics of the processor, refer to the
PC7450 RISC Microprocessor Family Reference Manual.
Screening
•
Full Military Temperature Range (T
c
= -55°C, T
J
= +125°C)
•
Industrial Temperature Range (T
c
= -40°C, T
J
= +110°C)
Visit our website: www.e2v.com
for the latest version of the datasheet
e2v semiconductors SAS 2007
PC7448 [Preliminary]
1. Overview
The PC7448 is the sixth implementation of fourth-generation (G4) microprocessors from Freescale
™
.
The PC7448 implements the full PowerPC 32 bits architecture and is targeted at networking and com-
puting systems applications. The PC7448 consists of a processor core and a 1 Mbyte L2.
Figure 1-1 on page 3
shows a block diagram of the PC7448. The core is a high-performance superscalar
design supporting a double-precision floating-point unit and a SIMD multimedia unit.
The memory storage subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to
main memory and other system resources.
2
0814B–HIREL–02/07
e2v semiconductors SAS 2007
e2v semiconductors SAS 2007
0814B–HIREL–02/07
Figure 1-1.
Additional Features
• Time Base Counter/Decrementer
Clock Multiplier
JTAG/COP Interface
Thermal/Power Management
Performance Monitor
Out-of-Order Issue of AltiVec Instr.
Completion Unit
96-Bit (3 Instructions)
Completion Queue
(16-Entry)
Instruction Unit
Branch Processing Unit
BTIC (128-Entry)
BHT (2048-Entry)
CTR
Fetcher
Instruction Queue
(12-Word)
Instruction MMU
SRs
(Shadow)
128-Entry
ITLB
128-Bit (4 Instructions)
PC7448 Block Diagram
Tags
IBAT Array
LR
Dispatch
Unit
Data MMU
SRs
(Original)
VR Issue
(4-Entry/2-Issue)
GPR Issue
(6-Entry/3-Issue)
FPR Issue
(2-Entry/1-Issue)
128-Entry
DTLB
Tags
32-Kbyte
I Cache
32-Kbyte
D Cache
DBAT Array
Reservation
Stations (2-Entry)
Completes up
to th ree
instructions
per clock
VR File
16 Rename
Buffers
Vector
Touch
Queue
GPR File
16 Rename
Buffers
EA
Load/Store Unit
Vector Touch Engine
+ (EA Calculation)
Finished
Stores
L1 Castout
PA
FPR File
16 Rename
Buffers
Reservation
Stations (2)
Reservation
Stations (2)
Reservation
Reservation
Reservation
Station
Station
Station
Reservation Reservation Reservation Reservation
Station
Station
Station
Station
Integer
Unit 2
x÷
Integer
Integer
Integer
Unit 122
Unit
Unit
(3)
+++
Floating-
Point Unit
+ x÷
FPSCR
L1 Push
Completed
Stores
Vector
Permute
Unit
Vector
Integer
Unit 2
Vector
Integer
Unit 1
Vector
FPU
128-Bit
128-Bit
32-Bit
32-Bit
32-Bit
Load Miss
64-Bit
64-Bit
Memory Subsystem
PC7448 [Preliminary]
L1 Store Queue
(LSQ)
L1 Load Queue (LLQ)
L1 Load Miss (5)
1-Mbyte Unified L2 Cache Controller
System Bus Interface
Load
Queue (11)
Bus Store Queue
Castout
Queue (5) /
Push
Queue (6)
1
L1 Service
Queues
Line
Block 0 (32-Byte)
Tags Status
Block 1 (32-Byte)
Status
L2 Prefetch (3)
Instruction Fetch (2)
Cacheable Store Miss (2)
L2 Store Queue (L2SQ)
Snoop Push/
L1 Castouts
Interventions
(4)
Bus Accumulator
Notes: The castout Queue and Push Queue share resources such for a combined total of 6 entries.
The castout Queue itself is limited to 5 entries, ensuring 1 entry will be available for a push.
36-Bit
Address Bus
64-Bit
Data Bus
3
PC7448 [Preliminary]
Note that the PC7448 is a footprint-compatible, drop-in replacement in an PC7447A application if the
core voltages are identical.
2. Features
This section summarizes features of the PC7448 implementation of the PowerPC architecture.
Major features of the PC7448 are as follows:
• High-performance, superscalar microprocessor
Up to four instructions can be fetched from the instruction cache at a time
Up to three instructions plus a branch instruction can be dispatched to the issue queues at a time
Up to 12 instructions can be in the Instruction Queue (IQ)
Up to 16 instructions can be at some stage of execution simultaneously
Single-cycle execution for most instructions
One instruction per clock cycle throughput for most instructions
Seven-stage pipeline control
• Eleven independent execution units and three register files
Branch Processing Unit (BPU) features static and dynamic branch prediction
– 128-entry (32-set, four-way set-associative) Branch Target Instruction Cache (BTIC), a
cache of branch instructions that have been encountered in branch/loop code sequences. If
a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than
it can be made available from the instruction cache. Typically, a fetch that hits the BTIC
provides the first four instructions in the target stream
– 2048-entry Branch History Table (BHT) with 2 bits per entry for four levels of prediction: not
taken, strongly not taken, taken, and strongly taken
– Up to three outstanding speculative branches
– Branch instructions that do not update the count register (CTR) or Link Register (LR) are
often removed from the instruction stream
– Eight-entry link register stack to predict the target address of branch conditional to link
register (bclr) instructions
Four Integer Units (IUs) that share 32 GPRs for integer operands
– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except
multiply, divide, and move to/from special-purpose register instructions
– IU2 executes miscellaneous instructions, including the CR logical operations, integer
multiplication and division instructions, and move to/from special-purpose register
instructions
Five-stage FPU and 32-entry FPR file
– Fully IEEE
®
754-1985 – compliant FPU for both single- and double-precision operations
– Supports non-IEEE mode for time-critical operations
– Hardware support for denormalized numbers
– Thirty-two 64 bits FPRs for single or double-precision operands
Four vector units and 32-entry Vector Register file (VRs).
4
0814B–HIREL–02/07
e2v semiconductors SAS 2007
PC7448 [Preliminary]
– Vector Permute Unit (VPU)
– Vector Integer Unit 1 (VIU1) handles short-latency AltiVec
®
integer instructions, such as
vector add instructions (for example,
vaddsbs, vaddshs,
and
vaddsws)
– Vector Integer Unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as
vector multiply add instructions (for example,
vmhaddshs, vmhraddshs,
and
vmladduhm)
– Vector Floating-point Unit (VFPU)
Three-stage Load/Store Unit (LSU)
– Supports integer, floating-point, and vector instruction load/store traffic
– Four-entry Vector Touch Queue (VTQ) supports all four architected AltiVec data stream
operations
– Three-cycle GPR and AltiVec load latency (byte, half word, word, vector) with one-cycle
throughput
– Four-cycle FPR load latency (single, double) with one-cycle throughput
– No additional delay for misaligned access within double-word boundary
– A dedicated adder calculates Effective Addresses (EAs)
– Supports store gathering
– Performs alignment, normalization, and precision conversion for floating-point data
– Executes cache control and TLB instructions
– Performs alignment, zero padding, and sign extension for integer data
– Supports hits under misses (multiple outstanding misses)
– Supports both big and little-endian modes, including misaligned little-endian accesses
• Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,
respectively, in a cycle. Instruction dispatch requires the following:
Instructions can only be dispatched from the three lowest IQ entries, IQ0, IQ1, and IQ2
A maximum of three instructions can be dispatched to the issue queues per clock cycle
Space must be available in the CQ for an instruction to dispatch (this includes instructions that are
assigned a space in the CQ but not in an issue queue)
• Rename buffers
16 GPR rename buffers
16 FPR rename buffers
16 VR rename buffers
• Dispatch unit
Decode/dispatch stage fully decodes each instruction
• Completion unit
Retires an instruction from the 16-entry Completion Queue (CQ) when all instructions ahead of it
have been completed, the instruction has finished executing, and no exceptions are pending
Guarantees sequential programming model (precise exception model)
Monitors all dispatched instructions and retires them in order
Tracks unresolved branches and flushes instructions after a mispredicted branch
5
0814B–HIREL–02/07
e2v semiconductors SAS 2007
京公网安备 11010802033920号
EEWORLD
