FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
ICS841608I
G
ENERAL
D
ESCRIPTION
The ICS841608I is an optimized PCIe and sRIO
IC
S
clock generator and member of the HiPerClocks™
HiPerClockS™
family of high-performance clock solutions from IDT.
The device uses a 25MHz parallel cr ystal to
generate 100MHz and 125MHz clock signals,
replacing solutions requiring multiple oscillator and fanout buffer
solutions. The device has excellent phase jitter (<1ps rms)
suitable for clock components requiring precise and low-jitter
PCIe or sRIO or both clock signals. Designed for telecom,
networking and industrial applications, the ICS841608I can also
drive the high-speed sRIO and PCIe SerDes clock inputs of
communication processors, DSPs, switches and bridges.
F
EATURES
• Eight HCSL outputs: configurable for PCIe (100MHz)
and sRIO (125MHz) clock signals
• Selectable crystal oscillator interface, 25MHz,
18pF parallel resonant crystal or LVCMOS/LVTTL
single-ended reference clock input
• Supports the following output frequencies:
100MHz or 125MHz
• VCO: 500MHz
• PLL bypass and output enable
• PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant
• RMS phase jitter @125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.37ps (typical)
• Full 3.3V power supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard and (RoHs 5) lead-free (RoHS 6)
packages
B
LOCK
D
IAGRAM
XTAL_IN
P
IN
A
SSIGNMENT
REF_SEL
BYPASS
REF_IN
OSC
XTAL_OUT
REF_IN
Pulldown
0
1
Q0
nQ0
FSEL
IREF
GND
V
DDA
V
DD
FemtoClock
PLL
1
VCO = 500MHz
0
÷N
÷4
÷5
(default)
Q1
XTAL_IN
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
GND
Q2
nQ2
Q3
nQ3
V
DD
Q4
nQ4
V
DD
nQ7
Q7
nQ6
Q6
GND
nQ5
Q5
nQ1
Q2
REF_SEL
Pulldown
M = ÷20
IREF
BYPASS
Pulldown
FSEL
Pulldown
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
MR/nOE
Pulldown
nQ2
Q3
nQ3
XTAL_OUT
MR/nOE
V
DD
Q0
nQ0
Q1
nQ1
ICS841608I
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
IDT
™
/ ICS
™
HCSL CLOCK GENERATOR
1
ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
Name
XTAL_IN,
XTAL_OUT
MR/nOE
Type
Input
Description
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Active HIGH master reset. Active LOW output enable. When logic HIGH, the
internal dividers are reset and the outputs are in high impedance (Hi-Z).
Pulldown
When logic LOW, the internal dividers and the outputs are enabled.
Asynchronous function. LVCMOS/LVTTL interface levels. See Table 3C.
Core supply pins.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Power supply ground.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3A.
HCSL current reference resistor output. An external fixed precision resistor
(475
Ω
) from this pin to ground provides a reference current used for
differential current-mode Qx/nQx clock outputs.
Selects PLL operation/PLL bypass operation. Asynchronous function.
Pulldown
LVCMOS/LVTTL interface levels. See Table 3B.
Analog supply pin.
Reference select. Selects the input reference source. See Table 3D.
Pulldown
LVCMOS/LVTTL interface levels.
Pulldown LVCMOS/LVTTL PLL reference clock input.
3
4, 14,
24, 31
5, 6
7, 8
9, 19, 32
10, 11
12, 13
15, 16
17, 18
20, 21
22, 23
25
26
27
28
29
30
Input
V
DD
Q0, nQ0
Q1, nQ1
GND
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
FSEL
IREF
BYPASS
V
DDA
REF_SEL
REF_IN
Power
Output
Output
Power
Output
Output
Output
Output
Output
Output
Input
Output
Input
Power
Input
Input
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
T
ABLE
3A. FSEL F
UNCTION
T
ABLE
(f
REF
= 25MH
Z
)
Input
FSEL
0
1
N
5
4
Outputs
Q0:7/nQ0:7
VCO/5 (100MHz) PCIe (default)
VCO/4 (125MHz) sRIO
T
ABLE
3B. BYPASS F
UNCTION
T
ABLE
Input
BYPASS
0
1
PLL Configuration
PLL enabled (default)
PLL bypassed (f
OUT
= f
REF
÷ N)
T
ABLE
3C. MR/nOE F
UNCTION
T
ABLE
Input
MR/nOE
0
1
Function
Outputs enabled (default)
Device reset, outputs disabled (high-impedance)
T
ABLE
3D. REF_SEL F
UNCTION
T
ABLE
Input
REF_SEL
0
1
Input Reference
XTAL (default)
REF_IN
IDT
™
/ ICS
™
HCSL CLOCK GENERATOR
2
ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
37°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.15
3.135
Typical
3. 3
3.3
3.3
Maximum
3.465
V
DD
3.465
87
15
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
REF_IN, REF_SEL,
BYPASS, MR/nOE,
FSEL
REF_IN, REF_SEL,
BYPASS, MR/nOE,
FSEL
V
DD
= V
IN
= 3.465V
Test Conditions
Minimum Typical
2
-0.3
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
I
IL
Input Low Current
V
DD
= 3.465V, V
IN
= 0V
-5
µA
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
Test Conditions
Minimum
Typical
25
50
7
Maximum
Units
MHz
Ω
pF
Fundamental
IDT
™
/ ICS
™
HCSL CLOCK GENERATOR
3
ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
Parameter
Output Frequency
RMS Phase Jitter (Random); NOTE 1
Test Conditions
VCO/5
VCO/4
100MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
100MHz, (1.2MHz – 50MHz),
10
6
samples, 25MHz crystal input
125MHz, (1.2MHz – 62.5MHz),
10
6
samples, 25MHz crystal input
100MHz, 10
6
samples,
25MHz crystal input
125MHz, 10
6
samples,
25MHz crystal input
Minimum
Typical
100
125
0.39
0.37
24.36
23.76
2.44
2.37
50
105
0.6
0.6
-100
-300
250
550
140
48
500
52
4
4
100
1150
Maximum
Units
MHz
MHz
ps
ps
ps
ps
ps
rms
ps
rms
ps
ps
V/ns
V/ns
mV
mV
mV
mV
mV
%
ps
t
jit(Ø)
T
j
Phase Jitter Peak-to-Peak; NOTE 2
T
REFCLK_HF_RMS
Phase Jitter RMS; NOTE 3
t
jit(cc)
t
sk(o)
Rise Edge
Rate
Fall Edge Rate
V
RB
V
MAX
V
MIN
V
CROSS
ΔV
CROSS
odc
T
STABLE
Cycle-to-Cycle Jitter; NOTE 4
Output Skew; NOTE 4, 5
Rising Edge Rate; NOTE 6, 7
Falling Edge Rate; NOTE 6, 7
Ringback Voltage; NOTE 6, 8
Absolute Max. Output Voltage; NOTE 9, 10
Absolute Min. Output Voltage; NOTE 9, 11
Absolute Crossing Voltage;
NOTE 9, 12, 13
Total Variation of V
Cross
over all edges;
NOTE 9, 12, 14
Output Duty Cycle; NOTE 6, 15
Power-up Stable Clock Output; NOTE 6, 8
t
L
PLL Lock Time
90
ms
NOTE: All specifications are taken at 100MHz and 125MHz.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: RMS jitter after applying system transfer function. See IDT Application Note,
PCI Express Reference Clock Requirements.
Maximum
limit for PCI Express is 86ps peak-to-peak.
NOTE 3: RMS jitter after applying system transfer function. The pole frequencies for H1 and H2 for PCIe Gen 2 are 8-16MHz and 5-16MHz.
See IDT Application Note,
PCI Express Reference Clock Requirements.
Maximum limit for PCI Express Generation 2 is 3.1ps rms.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 6: Measurement taken from differential waveform.
NOTE 7: Measurement from -150mV to +150mV on the differential waveform (derived from Qx minus nQx).
The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the
differential zero crossing. See Parameter Measurement Information Section.
NOTE 8: T
STABLE
is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the V
RB
±100 differential range. See Parameter Measurement Information Section.
NOTE 9: Measurement taken from single ended waveform.
NOTE 10: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 11: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 12: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section.
NOTE 13: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
Refers to all crossing points for this measurement. See Parameter Measurement Information Section.
NOTE 14: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the V
CROSS
for any par ticular system. See Parameter Measurement Information Section.
NOTE 15: Input duty cycle must be 50%.
IDT
™
/ ICS
™
HCSL CLOCK GENERATOR
4
ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
T
YPICAL
P
HASE
N
OISE AT
100MH
Z
100MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.39ps (typical)
➤
Filter
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
➤
Phase Noise Result by adding
Filter to raw data
O
FFSET
F
REQUENCY
(H
Z
)
T
YPICAL
P
HASE
N
OISE AT
125MH
Z
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.37ps (typical)
➤
Filter
➤
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
➤
Phase Noise Result by adding
Filter to raw data
O
FFSET
F
REQUENCY
(H
Z
)
IDT
™
/ ICS
™
HCSL CLOCK GENERATOR
5
➤
ICS841608AKI REV. A JUNE 18, 2008
京公网安备 11010802033920号
EEWORLD
