91305AGILF datasheet, PDF - EEWORLD Datasheet

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91305AGILF: Description91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8; Categorysemiconductor logic; File Size154KB，9 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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91305AGILF Overview

91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8

91305AGILF Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	8
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.6 V
Minimum supply/operating voltage	3 V
Rated supply voltage	3.3 V
Processing package description	4.40 MM, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-8
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
packaging shape	RECTANGULAR
Package Size	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.6500 mm
terminal coating	MATTE TIN
Terminal location	DUAL
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
series	91305
Enter conditions	STANDARD
Logic IC type	PLL BASED CLOCK DRIVER
Number of inverted outputs	0.0
Real output number	4
Maximum same-side bending	0.2500 ns
Max-Min frequency	133 MHz

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DATASHEET

HIGH PERFORMANCE COMMUNICATION BUFFER

ICS91305I

Description

The ICS91305I is a high performance, low skew, low jitter

clock driver. It uses a phase lock loop (PLL) technology to

align, in both phase and frequency, the REF input with the

CLKOUT signal. It is designed to distribute high speed

clocks in communication systems operating at speeds from

10 to 133 MHz.

ICS91305I is a zero delay buffer that provides

synchronization between the input and output. The

synchronization is established via CLKOUT feed back to the

input of the PLL. Since the skew between the input and

output is less than +/- 350 pS, the part acts as a zero delay

buffer.

The ICS91305I comes in an eight pin 150 mil SOIC

package. It has five output clocks. In the absence of REF

input, will be in the power down mode. In this mode, the PLL

is turned off and the output buffers are pulled low. Power

down mode provides the lowest power consumption for a

standby condition.

Features

•

Zero input - output delay

Frequency range 10 - 133 MHz (3.3V)

5V tolerant input REF

High loop filter bandwidth ideal for Spread Spectrum

applications

Less than 200 ps Jitter between outputs

Skew controlled outputs

Skew less than 250 ps between outputs

Available in 8 pin 150 mil SOIC & 173 mil TSSOP

packages

•

3.3V ±10% operation

•

Supports industrial temperature range -40°C to 85°C

Block Diagram

IDT®

HIGH PERFORMANCE COMMUNICATION BUFFER

ICS91305I

REV G 090612

91305AGILF Related Products

	91305AGILF	91305AMILFT	ICS91305I
Description	91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8	91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8	91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
Number of functions	1	1	1
Number of terminals	8	8	8
Maximum operating temperature	85 Cel	85 Cel	85 Cel
Minimum operating temperature	-40 Cel	-40 Cel	-40 Cel
Maximum supply/operating voltage	3.6 V	3.6 V	3.6 V
Minimum supply/operating voltage	3 V	3 V	3 V
Rated supply voltage	3.3 V	3.3 V	3.3 V
Processing package description	4.40 MM, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-8	4.40 MM, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-8	4.40 MM, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-8
Lead-free	Yes	Yes	Yes
EU RoHS regulations	Yes	Yes	Yes
state	ACTIVE	ACTIVE	ACTIVE
packaging shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package Size	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
surface mount	Yes	Yes	Yes
Terminal form	GULL WING	GULL WING	GULL WING
Terminal spacing	0.6500 mm	0.6500 mm	0.6500 mm
terminal coating	MATTE TIN	MATTE TIN	MATTE TIN
Terminal location	DUAL	DUAL	DUAL
Packaging Materials	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
series	91305	91305	91305
Enter conditions	STANDARD	STANDARD	STANDARD
Logic IC type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Number of inverted outputs	0.0	0.0	0.0
Real output number	4	4	4
Maximum same-side bending	0.2500 ns	0.2500 ns	0.2500 ns
Max-Min frequency	133 MHz	133 MHz	133 MHz

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