DATASHEET
HIGH PERFORMANCE COMMUNICATION BUFFER
ICS91305I
Description
The ICS91305I is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the REF input with the
CLKOUT signal. It is designed to distribute high speed
clocks in communication systems operating at speeds from
10 to 133 MHz.
ICS91305I is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to the
input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
The ICS91305I comes in an eight pin 150 mil SOIC
package. It has five output clocks. In the absence of REF
input, will be in the power down mode. In this mode, the PLL
is turned off and the output buffers are pulled low. Power
down mode provides the lowest power consumption for a
standby condition.
Features
•
•
•
•
•
•
•
•
Zero input - output delay
Frequency range 10 - 133 MHz (3.3V)
5V tolerant input REF
High loop filter bandwidth ideal for Spread Spectrum
applications
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 pin 150 mil SOIC & 173 mil TSSOP
packages
•
3.3V ±10% operation
•
Supports industrial temperature range -40°C to 85°C
Block Diagram
IDT®
HIGH PERFORMANCE COMMUNICATION BUFFER
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ICS91305I
REV G 090612
ICS91305I
HIGH PERFORMANCE COMMUNICATION BUFFER
Pin Configuration
Pin Descriptions
IDT®
HIGH PERFORMANCE COMMUNICATION BUFFER
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ICS91305I
REV G 090612
ICS91305I
HIGH PERFORMANCE COMMUNICATION BUFFER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS91305I. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics at 3.3V
DC Characteristics
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low
Voltage
1
Output High
Voltage
1
Power Down
Supply Current
Supply Current
Notes:
1.Guaranteed by design and characterization. Not subject to 100% test.
2.All Skew specifications are mesured with a 50Ω transmission line, load teminated with 50Ω to 1.4V.
3.Duty cycle measured at 1.4V.
4.Skew measured at 1.4V on rising edges. Loading must be equal on outputs.
SYMBOL
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
I
DD
TEST CONDITIONS
MIN
TYP
MAX
0.8
UNITS
V
V
2.0
V
IN
=0V
V
IN
=V
DD
I
OL
= 12mA
I
OH
= -12mA
REF = 0 MHz
Unloaded oututs at 66.66 MHz
SEL inputs at V
DD
or GND
2.4
19
0.10
0.25
2.9
0.3
30.0
100.0
80.0
100.0
250.0
0.4
µA
µA
V
V
µA
mA
IDT®
HIGH PERFORMANCE COMMUNICATION BUFFER
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ICS91305I
REV G 090612
ICS91305I
HIGH PERFORMANCE COMMUNICATION BUFFER
Switching Characteristics
PARAMETER
Output period
Input period
Duty Cycle
1
Duty Cycle
1
Rise Time
1
Fall Time
1
Delay, REF Rising
Edge to CLKOUT
Rising Edge
1, 2
Output to Output
Skew
1
Device to Device
Skew
1
Cycle to Cycle
Jitter
1
PLL Lock Time
1
Jitter; Absolute
Jitter
1
Jitter; 1 - Sigma
1
SYMBOL
t1
t1
Dt1
Dt2
tr1
tf1
Dr1
Tskew
Tdsk-Tdsk
Tcyc-Tcyc
t
LOCK
Tjabs
Tj1s
CONDITION
With CL=30pF
With CL=30pF
Measured at 1.4V; CL=30pF
Measured at VDD/2 Fout
<66.6MHz
Measured between 0.8V and 2.0V:
CL=30pF
Measured between 2.0V and 0.8V;
CL=30pF
Measured at 1.4V
All outputs equally loaded,
CL=20pF
Measured at VDD/2 on the
CLKOUT pins of devices
Measured at 66.66 MHz, loaded
outputs
Stable power supply, valid clock
presented on REF pin
@ 10,000 cycles
C
L
= 30pF
@ 10,000 cycles
C
L
= 30pF
-200
70
14
0
MIN
100.00
(10)
100.00
(10)
40.0
45
50
50
1.2
1.2
0
TYP
MAX
7.5
(133)
7.5
(133)
60
55
1.5
1.5
±350
250
700
200
1.0
200
60
UNITS
ns
(MHz)
ns
(MHz)
%
%
ns
ns
ps
ps
ps
ps
ms
ps
ps
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. REF input has a threshold voltage of 1.4V
3. All parameters expected with loaded outputs
IDT®
HIGH PERFORMANCE COMMUNICATION BUFFER
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ICS91305I
REV G 090612
ICS91305I
HIGH PERFORMANCE COMMUNICATION BUFFER
Output to Output Skew
The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of
the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase
difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; and if the CLK(1-4) is more loaded than
CLKOUT, CLK(1-4) will lag the CLKOUT.
Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause them to
have different rise times and different times crossing the measurement thresholds.
Timing diagrams with different loading configurations
IDT®
HIGH PERFORMANCE COMMUNICATION BUFFER
5
ICS91305I
REV G 090612
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