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ICS854S006I

Description
Low Skew, 1-to-6, Differential-to - LVDS Fanout Buffer One differential clock input pair
File Size191KB,15 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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ICS854S006I Overview

Low Skew, 1-to-6, Differential-to - LVDS Fanout Buffer One differential clock input pair

Low Skew, 1-to-6, Differential-to-
LVDS Fanout Buffer
ICS854S006I
DATA SHEET
G
ENERAL
D
ESCRIPTION
The ICS854S006I is a low skew, high perfor-
mance 1-to-6 Differential-to-LVDS Fanout Buffer.
HiPerClockS™
The CLK, nCLK pair can accept most standard dif-
ferential input levels. The ICS854S006I is charac-
terized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output skew characteristic s
make the ICS854S006I ideal for those clock distribution
applications demanding well defined performance and
repeatability.
F
EATURES
Six differential LVDS outputs
One differential clock input pair
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 1.7GHz
Translates any single ended input signal to LVDS levels
with resistor bias on nCLK input
Output skew: 55ps (maximum)
Propagation delay: 850ps (maximum)
Additive phase jitter, RMS: 0.067ps (typical)
Full 3.3V or 2.5V power supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
B
LOCK
D
IAGRAM
Q0
nQ0
CLK
Pullup
nCLK
Pulldown
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
P
IN
A
SSIGNMENT
nCLK
CLK
V
DD
V
DDO
Q0
nQ0
GND
Q1
nQ1
V
DDO
Q2
nQ2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
GND
V
DD
V
DDO
nQ5
Q5
GND
nQ4
Q4
V
DDO
nQ3
Q3
ICS854S006I
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm package body
G Package
Top View
ICS854S006AGI REVISION B JANUARY 18, 2010
1
©2010
Integrated Device Technology, Inc.

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Description Low Skew, 1-to-6, Differential-to - LVDS Fanout Buffer One differential clock input pair Low Skew, 1-to-6, Differential-to - LVDS Fanout Buffer One differential clock input pair
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