Low Skew, 1-to-6, Differential-to-
LVDS Fanout Buffer
ICS854S006I
DATA SHEET
G
ENERAL
D
ESCRIPTION
The ICS854S006I is a low skew, high perfor-
mance 1-to-6 Differential-to-LVDS Fanout Buffer.
HiPerClockS™
The CLK, nCLK pair can accept most standard dif-
ferential input levels. The ICS854S006I is charac-
terized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output skew characteristic s
make the ICS854S006I ideal for those clock distribution
applications demanding well defined performance and
repeatability.
F
EATURES
•
Six differential LVDS outputs
•
One differential clock input pair
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 1.7GHz
•
Translates any single ended input signal to LVDS levels
with resistor bias on nCLK input
•
Output skew: 55ps (maximum)
•
Propagation delay: 850ps (maximum)
•
Additive phase jitter, RMS: 0.067ps (typical)
•
Full 3.3V or 2.5V power supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
B
LOCK
D
IAGRAM
Q0
nQ0
CLK
Pullup
nCLK
Pulldown
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
P
IN
A
SSIGNMENT
nCLK
CLK
V
DD
V
DDO
Q0
nQ0
GND
Q1
nQ1
V
DDO
Q2
nQ2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
GND
V
DD
V
DDO
nQ5
Q5
GND
nQ4
Q4
V
DDO
nQ3
Q3
ICS854S006I
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm package body
G Package
Top View
ICS854S006AGI REVISION B JANUARY 18, 2010
1
©2010
Integrated Device Technology, Inc.
ICS854S006I Data Sheet
LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 22
4, 10, 15, 21
5, 6
7, 18, 23, 24
8, 9
11, 12
13, 14
16, 17
19, 20
Name
nCLK
CLK
V
DD
V
DDO
Q0, nQ0
GND
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Input
Input
Power
Power
Output
Power
Output
Output
Output
Output
Output
Type
Pullup
Description
Non-inver ting differential clock input.
Positive supply pins.
Output supply pins.
Differential output pair. LVDS interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Pulldown Inver ting differential clock input.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0:Q5
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0:nQ5
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
ICS854S006AGI REVISION B JANUARY 18, 2010
2
©2010
Integrated Device Technology, Inc.
ICS854S006I Data Sheet
LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
4.6V
-0.5V to V
DD
+ 0.5 V
10mA
15mA
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
70°C/W (0 mps)
Storage Temperature, T
STG
(Junction-to-Ambient)
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
55
105
Units
V
V
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
55
102
Units
V
V
mA
mA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
Parameter
CLK
I
IH
Input High Current
nCLK
CLK
I
IL
Input Low Current
nCLK
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage;
V
CMR
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V
NOTE 2: Common mode voltage is defined as V
IH
.
V
PP
Test Conditions
V
DD
= V
IN
= 3.465V
or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= V
IN
= 3.465V
or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
-150
-10
0.15
GND + 0.5
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
10
150
Units
µA
µA
µA
µA
V
V
ICS854S006AGI REVISION B JANUARY 18, 2010
3
©2010
Integrated Device Technology, Inc.
ICS854S006I Data Sheet
LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.28
Test Conditions
Minimum
326
Typical
Maximum
526
50
1.44
50
Units
mV
mV
V
mV
NOTE: Please refer to Parameter Measurement Information for output information.
T
ABLE
4E. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
1.1
Test Conditions
Minimum
305
Typical
Maximum
505
50
1.45
50
Units
mV
mV
V
mV
V
OS
Magnitude Change
Δ
V
OS
NOTE: Please refer to Parameter Measurement Information for output information.
NOTE: Maximum value is a design target spec.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Output Rise/Fall Time
300
Test Conditions
Minimum
Typical
Maximum Units
1.7
850
55
622.08MHz,
Integration Range: 12kHz – 20MHz
20% to 80%
50
0.067
250
GH z
ps
ps
ps
ps
t
PD
t
sk(o)
t
jit
t
R
/ t
F
odc
Output Duty Cycle
≤
1.2GHz
47
53
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured from at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Output Rise/Fall Time
300
Test Conditions
Minimum
Typical
Maximum
1.7
800
55
622.08MHz,
Integration Range: 12kHz – 20MHz
20% to 80%
≤
1.2GHz
50
47
0.067
250
53
Units
GH z
ps
ps
ps
ps
%
t
PD
t
sk(o)
t
jit
t
R
/ t
F
odc
Output Duty Cycle
For NOTES, see Table 5A.
ICS854S006AGI REVISION B JANUARY 18, 2010
4
©2010
Integrated Device Technology, Inc.
ICS854S006I Data Sheet
LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc
value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter
@
622.08MHz (12kHz to 20MHz)
= 0.067ps (typical)
SSB P
HASE
N
OISE
dBc/H
Z
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
ICS854S006AGI REVISION B JANUARY 18, 2010
5
©2010
Integrated Device Technology, Inc.
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