Integrated
Circuit
Systems, Inc.
ICS85310-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
F
EATURES
•
2 differential 2.5V/3.3V LVPECL / ECL bank outputs
•
2 differential clock input pairs
•
CLKx, nCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 700MHz
•
Translates any single ended input signal to 3.3V LVPECL
levels with resistor bias on nCLKx input
•
Output skew: 25ps (typical)
•
Part-to-part skew: 270ps (typical)
•
Propagation delay: 1.7ns (typical)
•
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -2.375V to -3.8V
•
-40°C to 85°C ambient operating temperature
•
Pin compatible with MC100LVEP210
G
ENERAL
D
ESCRIPTION
The ICS85310-21 is a low skew, high perfor-
mance dual 1-to- 5 Differential-to-2.5V/3.3V
HiPerClockS™
ECL/LVPECL Fanout Buffer and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The CLKx, nCLKx pairs
can accept most standard differential input levels.
The ICS85310-21 is characterized to operate from either a
2.5V or a 3.3V power supply. Guaranteed output and part-
to-part skew characteristics make the ICS85310-21 ideal
for those clock distribution applications demanding well
defined performance and repeatability.
,&6
B
LOCK
D
IAGRAM
CLKA
nCLKA
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
P
IN
A
SSIGNMENT
nQA0
nQA1
nQA2
32 31 30 29 28 27 26 25
V
CC
nc
CLKA
nCLKA
nc
CLKB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
V
CCO
nQB4
QB4
nQB3
QB3
nQB2
QB2
V
CCO
V
CCO
V
CCO
ICS85310-21
QA0
QA1
QA2
24
23
22
21
20
19
18
17
QA3
nQA3
QA4
nQA4
QB0
nQB0
QB1
nQB1
CLKB
nCLKB
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
nCLKB
V
EE
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
85310AY-21
www.icst.com/products/hiperclocks.html
1
REV. A MAY 30, 2002
Integrated
Circuit
Systems, Inc.
ICS85310-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
Type
Power
Unused
Input
Input
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pullup
Pullup
Description
Positive supply pin.
No connect.
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
Inver ting differential clock input.
Negative supply pin.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Pulldown Non-inver ting differential clock input.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 5
3
4
6
7
8
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
Name
V
CC
nc
CLKA
nCLKA
CLKB
nCLKB
V
EE
V
CCO
nQB4, QB4
nQB3, QB3
nQB2, QB2
nQB1, QB1
nQB0, QB0
nQA4, QA4
nQA3, QA3
nQA2, QA2
nQA1, QA1
nQA0, QA0
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
51
51
Test Conditions
Minimum
Typical
Maximum
4
Units
pF
KΩ
KΩ
T
ABLE
3. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLKA or CLKB
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLKA or nCLKB
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
QA0:QA4,
nQA0:nQA4,
QB0:QB4
nQB0:nQB4
LOW
HIGH
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
85310AY-21
www.icst.com/products/hiperclocks.html
2
REV. A MAY 30, 2002
Integrated
Circuit
Systems, Inc.
ICS85310-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
4.6V
-0.5V to V
CC
+ 0.5V
-0.5V to V
CCO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
, V
CCO
= 2.375V - 3.8V, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCO
I
EE
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
3.3
3.3
Maximum
3.8
3.8
30
Units
V
V
mA
T
ABLE
4B. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
, V
CCO
= 2.375V - 3.8V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLKA, CLKB
nCLKA, nCLKB
CLKA, CLKB
nCLKA, nCLKB
Test Conditions
V
CC
= V
IN
= 3.8V
V
CC
= V
IN
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
V
CC
= 3.8V, V
IN
= 0V
-5
-150
0.15
1.3
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
Peak-to-Peak Input Voltage
V
CMR
Common Mode Input Voltage; NOTE 1, 2
V
EE
+ 0.5
V
CC
- 0.85
V
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLKA, nCLKA and CLKB, nCLKB is V
CC
+ 0.3V.
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
, V
CCO
= 2.375V - 3.8V, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
V
SWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 1.0
V
CCO
- 1.7
0.85
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
85310AY-21
www.icst.com/products/hiperclocks.html
3
REV. A MAY 30, 2002
Integrated
Circuit
Systems, Inc.
ICS85310-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
Test Conditions
IJ 500MHz
Minimum
Typical
1.7
25
270
20% to 80%
20% to 80%
200
200
Maximum
700
2.2
50
550
700
700
53
Units
MHz
ns
ps
ps
ps
ps
%
T
ABLE
5A. AC C
HARACTERISTICS
,
V
CC
, V
CCO
= 2.375V - 3.8V, T
A
= -40°C
TO
85°C
Symbol
f
MAX
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise Time
Output Fall Time
t
PD
t
sk(o)
t
sk(pp)
t
R
t
F
odc
Output Duty Cycle
47
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
85310AY-21
www.icst.com/products/hiperclocks.html
4
REV. A MAY 30, 2002
Integrated
Circuit
Systems, Inc.
ICS85310-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V ECL/LVPECL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
CC
, V
CCO
SCOPE
Qx
LVPECL
V
CC
, V
CCO
= 2V
nQx
V
EE
= -0.375V
to
-1.8V
3.3V O
UTPUT
L
OAD
T
EST
C
IRCUIT
V
CC
nCLKA, nCLKB
V
CLKA, CLKB
PP
Cross Points
V
CMR
V
EE
D
IFFERENTIAL
I
NPUT
L
EVEL
85310AY-21
www.icst.com/products/hiperclocks.html
5
REV. A MAY 30, 2002
京公网安备 11010802033920号
EEWORLD
