IDT72V73260DA8 datasheet, PDF - EEWORLD Datasheet

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IDT72V73260DA8: DescriptionDigital Time Switch, PQFP144, 20 X 20 MM, 0.50 MM PITCH, TQFP-144; CategoryWireless rf/communication Telecom circuit; File Size194KB，26 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT72V73260DA8 Overview

Digital Time Switch, PQFP144, 20 X 20 MM, 0.50 MM PITCH, TQFP-144

IDT72V73260DA8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	20 X 20 MM, 0.50 MM PITCH, TQFP-144
Contacts	144
Reach Compliance Code	not_compliant
JESD-30 code	S-PQFP-G144
JESD-609 code	e0
length	20 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	144
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.6 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	DIGITAL TIME SWITCH
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	20 mm

IDT72V73260DA8 Preview

3.3 VOLT TIME SLOT INTERCHANGE

DIGITAL SWITCH

16,384

IDT72V73260

FEATURES:

•

16K x 16K non-blocking switching at 32.768Mb/s

32 serial input and output streams

Accepts single-bit single-data streams at 32.768Mb/s

Per-channel Variable Delay Mode for low-latency applications

Per-channel Constant Delay Mode for frame integrity applications

Automatic identification of ST-BUS

and GCI bus interfaces

Automatic frame offset delay measurement

Per-stream single data frame delay offset programming

Per-channel high-impedance output control

Direct microprocessor access to all internal memories

Memory block programming for quick setup

IEEE-1149.1 (JTAG) Test Port

3.3V Power Supply

Available in 144-pin (13mm x 13mm) Plastic Ball Grid Array

(PBGA) and 144-pin (20mm x 20mm) Thin Quad Flatpack (TQFP)

Operating Temperature Range -40°C to +85°C

DESCRIPTION:

The IDT72V73260 has a non-blocking switch capacity of 16,384 x 16,384

channels at 32.768Mb/s. With 32 inputs and 32 outputs, programmable per

stream control, and a variety of operating modes the IDT72V73260 is designed

for the TDM time slot interchange function in either voice or data applications.

Some of the main features of the IDT72V73260 are LOW power 3.3 Volt

operation, automatic ST-BUS

/GCI sensing, memory block programming,

simple microprocessor interface , JTAG Test Access Port (TAP) and per stream

programmable input offset delay, variable or constant throughput modes, output

enable and processor mode.

FUNCTIONAL BLOCK DIAGRAM

GND

RESET

ODE

TX0

RX0

RX1

Data Memory

MUX

TX1

Receive

Serial Data

Streams

Internal

Registers

RX31

Connection

Memory

Transmit

Serial Data

Streams

TX15

TX16/OEI0

TX17/OEI1

TX31/OEI15

Timing Unit

Microprocessor Interface

JTAG Port

C32i

F32i

R/W

A0-A15

DTA

D0-D15

TMS TDI TCK TDO

TRST

5932 drw01

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS

is a trademark of Mitel Corp.

JUNE 2004

DSC-5932/10



IDT72V73260 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 16,384 x 16,384

INDUSTRIAL TEMPERATURE RANGE

PIN CONFIGURATIONS

A1 BALL PAD CORNER

C32i

RESET

ODE

RX1

RX4

RX7

TX4

TX7

TX10

TX12

TX14

TX15

F32i

TMS

RX0

TDI

RX2

RX3

RX5

RX6

TX0

TX1

TX3

TX2

TX6

TX5

TX9

TX8

TX11

RX11

TX13

RX10

RX8

RX9

(1)

TDO

TCK

R/W

TRST

GND

RX15

VCC

RX14

RX18

RX13

RX17

RX12

RX16

GND

VCC

RX21

RX20

RX19

TX16/

OEI0

TX19/

OEI3

TX22/

OEI6

TX24/

OEI8

TX26/

OEI10

TX27/

OEI11

GND

VCC

RX22

TX17/

OEI1

TX20/

OEI4

TX31/

OEI15

TX30/

OEI14

TX29/

OEI13

RX23

TX18/

OEI2

TX21/

OEI5

TX23/

OEI7

TX25/

OEI9

TX28/

OEI12

A12

A11

A10

GND

A13

RX27

(1)

A15

DTA

D13

A14

RX30

RX26

D15

D11

D12

D10

RX31

RX29

RX28

RX25

RX24

D14

NOTE:

1. NC

5932 drw02

= No Connect.

PBGA: 1mm pitch, 13mm x13mm (BB144-1, order code: BB)

TOP VIEW

IDT72V73260 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 16,384 x 16,384

INDUSTRIAL TEMPERATURE RANGE

PIN CONFIGURATIONS (CONTINUED)

GND

TX15

TX14

TX13

TX12

GND

TX11

TX10

TX9

TX8

GND

TX7

TX6

TX5

TX4

GND

TX3

TX2

TX1

TX0

GND

RX7

RX6

RX5

RX4

RX3

RX2

RX1

RX0

ODE

RESET

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

108

107

106

105

104

103

102

101

100

RX8

RX9

RX10

RX11

RX12

RX13

RX14

RX15

RX16

RX17

RX18

RX19

RX20

RX21

RX22

RX23

GND

TX16/OEI0

TX17/OEI1

TX18/OEI2

TX19/OEI3

GND

TX20/OEI4

TX21/OEI5

TX22/OEI6

TX23/OEI7

GND

TX24/OEI8

TX25/OEI9

TX26/OEI10

TX27/OEI11

GND

TX28/OEI12

TX29/OEI13

TX30/OEI14

TX31/OEI15

GND

RX24

RX25

RX26

RX27

RX28

RX29

RX30

RX31

GND

VCC

GND

D10

D11

GND

D12

D13

5932 drw03

PIN 1

NOTE:

1. NC = No Connect.

GND

C32i

F32i

(1)

TMS

TDI

TDO

TCK

TRST

R/W

A10

A11

A12

A13

A14

A15

(1)

DTA

GND

D15

D14

TQFP: 0.50mm pitch, 20mm x 20mm (DA144-1, order code: DA)

TOP VIEW

IDT72V73260 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 16,384 x 16,384

INDUSTRIAL TEMPERATURE RANGE

PIN DESCRIPTION

SYMBOL

NAME

A0-15

Address 0 to 15

C32i

D0-15

DTA

Clock

Chip Select

Data Bus 0-15

Data Strobe

Data Transfer

Acknowledgment

Frame Evaluation

I/O

DESCRIPTION

I These address lines access all internal memories.

Serial clock for shifting data in/out on the serial data stream. This input accepts a 32.768 MHz clock.

This active LOW input is used by a microprocessor to activate the microprocessor port of IDT72V73260.

I/O These pins are the data bits of the microprocessor port.

I This active LOW input works in conjunction with

to enable the read and write operations and sets the

data bus lines (D0-D15).

Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then goes

high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required

to hold a HIGH level when the pin is in high-impedance.

This input can be used to measure delay in the data path by comparing the frame pulse, F32i, with this input.

F32i

GND

ODE

Frame Pulse

Ground

Output Drive Enable

This input accepts and automatically identifies frame synchronization signals formatted according to

ST-BUS

and GCI specifications.

Ground Rail

This is the output enable control for the TX serial outputs. When the ODE input is LOW and the Output Stand

By bit of the Control Register is LOW, all TX outputs are in a high-impedance state. If this input is HIGH, the TX

output drivers are enabled. However, each channel may still be put into a high-impedance state by using the

per-channel control bits in the Connection Memory.

This input puts the IDT72V73260 into a reset state that clears the device internal counters, registers and

brings TX0-31 and D0-D15 into a high-impedance state. The

RESET

pin must be held LOW for a minimum

of 20ns to properly reset the device.

This input controls the direction of the data bus lines (D0-D15) during a microprocessor access.

Serial data input stream. These streams have a data rate of 32.768Mb/s.

Provides the clock to the JTAG test logic.

JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up

when not driven.

JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state

when JTAG scan is not enabled.

JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal

pull-up when not driven.

Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is

pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW,

to ensure that the IDT72V73260 is in the normal functional mode.

Serial data output stream. These streams have a data rate of 32.768Mb/s.

When all 32 output streams are selected via Control Register, these pins are the output streams TX16 to TX31

and operate at 32.768Mb/s. When output enable function is selected, these pins reflect the active or

high-impedance status for the corresponding output stream Output Enable Indication0-15.

+3.3 Volt Power Supply.

RESET

Device Reset

R/W

RX0-31

TCK

TDI

TDO

TMS

TRST

Read/Write

Data Stream

Input 0 to 31

Test Clock

Test Serial Data In

Test Serial Data Out

Test Mode Select

Test Reset

TX0-15

TX Output 0 to 15

(Three-State Outputs)

TX16-31/ TX Output 16 to 31/

OEI0-15 Output Enable

Indication 0 to 15

(Three-State Outputs)

IDT72V73260 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 16,384 x 16,384

INDUSTRIAL TEMPERATURE RANGE

DESCRIPTION (CONTINUED)

The IDT72V73260 is capable of switching up to 16,384 x 16,384 channels

without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the

device maintains frame integrity in data applications and minimizes throughput

delay for voice applications on a per-channel basis.

The 32 serial input streams (RX) of the IDT72V73260 are run at 32.768Mb/s

allowing 512 channels per 125µs frame. The data rates on the output streams

(TX) are identical to those on the input streams (RX).

With two main operating modes, Processor Mode and Connection Mode, the

IDT72V73260 can easily switch data from incoming serial streams (Data

Memory) or from the controlling microprocessor via Connection Memory. As

control and status information is critical in data transmission, the Processor Mode

is especially useful when there are multiple devices sharing the input and output

streams.

With data coming from multiple sources and through different paths, data

entering the device is often delayed. To handle this problem, the IDT72V73260

has a Frame Evaluation feature to allow individual streams to be offset from the

frame pulse in half clock-cycle intervals up to +7.5 clock cycles.

The IDT72V73260 also provides a JTAG test access port, memory block

programming, a simple microprocessor interface and automatic ST-BUS

/GCI

sensing to shorten setup time, aid in debugging and ease use of the device

without sacrificing capabilities.

SERIAL DATA INTERFACE TIMING

For a 32.768Mb/s serial data rate , the master clock frequency will be running

at 32.768 MHz resulting in a single-bit per clock. The IDT72V73260 provides

two different interface timing modes, ST-BUS

or GCI.

The IDT72V73260 automatically detects the presence of an input frame

pulse and identifies it as either ST-BUS

or GCI. In ST-BUS

Mode, data is

clocked out on the falling edge and is clocked in on the subsequent rising-edge.

See Figure 14 for timing. In GCI Mode, data is clocked out on the rising edge

and is clocked in on the subsequent falling edge. See Figure 15 for timing.

INPUT FRAME OFFSET SELECTION

Input frame offset selection allows the channel alignment of individual input

streams to be offset with respect to the output stream channel alignment. Although

all input data comes in at the same speed, delays can be caused by variable

path serial backplanes and variable path lengths which may be implemented

in large centralized and distributed switching systems. Because data is often

delayed, this feature is useful in compensating for the skew between input

streams.

Each input stream can have its own delay offset value by programming the

frame input offset registers (FOR, Table 8). The maximum allowable skew is +7.5

master clock (C32i) periods forward with a resolution of ½ clock period, see

Table 9. The output frame cannot be adjusted.

SERIAL INPUT FRAME ALIGNMENT EVALUATION

The IDT72V73260 provides the Frame Evaluation input to determine

different data input delays with respect to the frame pulse F32i. A measurement

cycle is started by setting the Start Frame Evaluation bit of the Control Register

LOW for at least one frame. When the Start Frame Evaluation bit in the Control

the Complete Frame Evaluation bit of the Frame Alignment Register changes

from LOW to HIGH to signal that a valid offset measurement is ready to be read

from bits 0 to 12 of the Frame Alignment Register . The Start Frame Evaluation

bit must be set to zero before a new measurement cycle is started.

In ST-BUS

mode, the falling edge of the frame measurement signal (Frame

Evaluation) is evaluated against the falling edge of the ST-BUS

frame pulse.

In GCI mode, the rising edge of Frame Evaluation is evaluated against the rising

edge of the GCI frame pulse. See Table 7 and Figure 1 for the description of

the Frame Alignment Register.

MEMORY BLOCK PROGRAMMING

The IDT72V73260 provides users with the capability of initializing the entire

Connection Memory block in two frames. To set bits 14 and 15 of every

Connection Memory location, first program the desired pattern in the Block

Programming Data Bits (BPD 1-0), located in bits 7 and 8 of the Control Register.

The block programming mode is enabled by setting the Memory Block

Program bit of the Control Register HIGH. When the Block Programming Enable

bit of the Control Register is set to HIGH, the Block Programming data will be

loaded into the bits 14 and 15 of every Connection Memory location. The other

Connection Memory bits (bit 0 to bit 13) are loaded with zeros. When the memory

block programming is complete, the device resets the Block Programming

Enable, BPD 1-0 and Memory Block Program bits to zero.

FUNCTIONAL DESCRIPTION

DATA AND CONNECTION MEMORY

All data that comes in through the RX inputs go through a serial-to-parallel

conversion before being stored into internal Data Memory. The 8 KHz frame

pulse (F32i) is used to mark the 125µs frame boundaries and to sequentially

address the input channels in Data Memory.

Data output on the TX streams may come from either the serial input streams

(Data Memory) or from the microprocessor (Connection Memory). In the case

that RX input data is to be output, the addresses in Connection Memory are used

to specify a stream and channel of the input. The Connection Memory is setup

in such a way that each location corresponds to an output channel for each

particular stream. In that way, more than one channel can output the same data.

In Processor Mode, the microprocessor writes data to the Connection Memory

locations corresponding to the stream and channel that is to be output. The lower

half (8 least significant bits) of the Connection Memory is output every frame until

the microprocessor changes the data or mode of the channel. By using this

Processor Mode capability, the microprocessor can access input and output

time-slots on a per-channel basis.

The two most significant bits of the Connection Memory are used to control

per-channel mode of the out put streams. Specifically, the MOD1-0 bits are used

to select Processor Mode, Constant or Variable delay Mode, and the high-

impedance state of output drivers. If the MOD1-0 bits are set to 1-1 accordingly,

only that particular output channel (8 bits) will be in the high-impedance state.

If however, the ODE input pin is LOW and the Output Standby Bit in the Control

particular channel in Connection Memory has enabled the output for that

channel. In other words, the ODE pin and Output Stand By control bit are master

output enables for the device (See Table 3).

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IDT72V73260DA8 Related Products

	IDT72V73260DA8	IDT72V73260BBG	IDT72V73260DA	72V73260BB	72V73260DA	72V73260DA8
Description	Digital Time Switch, PQFP144, 20 X 20 MM, 0.50 MM PITCH, TQFP-144	Digital Time Switch, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144	Digital Time Switch, PQFP144, 20 X 20 MM, 0.50 MM PITCH, TQFP-144	Digital Time Switch, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144	Digital Time Switch, PQFP144, 20 X 20 MM, 0.50 MM PITCH, TQFP-144	Digital Time Switch, PQFP144, 20 X 20 MM, 0.50 MM PITCH, TQFP-144
Is it lead-free?	Contains lead	Lead free	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	conform to	incompatible	incompatible	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QFP	BGA	QFP	BGA	QFP	QFP
package instruction	20 X 20 MM, 0.50 MM PITCH, TQFP-144	13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144	20 X 20 MM, 0.50 MM PITCH, TQFP-144	BGA, BGA144,12X12,40	20 X 20 MM, 0.50 MM PITCH, TQFP-144	LFQFP,
Contacts	144	144	144	144	144	144
Reach Compliance Code	not_compliant	compliant	not_compliant	_compli	_compli	compli
JESD-30 code	S-PQFP-G144	S-PBGA-B144	S-PQFP-G144	S-PBGA-B144	S-PQFP-G144	S-PQFP-G144
JESD-609 code	e0	e1	e0	e0	e0	e0
length	20 mm	13 mm	20 mm	13 mm	20 mm	20 mm
Humidity sensitivity level	3	3	3	3	3	3
Number of functions	1	1	1	1	1	1
Number of terminals	144	144	144	144	144	144
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	BGA	LFQFP	BGA	LFQFP	LFQFP
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240	260	240	225	225	240
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.97 mm	1.6 mm	1.97 mm	1.6 mm	1.6 mm
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES
Telecom integrated circuit types	DIGITAL TIME SWITCH	DIGITAL TIME SWITCH	DIGITAL TIME SWITCH	DIGITAL TIME SWITCH	DIGITAL TIME SWITCH	DIGITAL TIME SWITCH
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)	TIN SILVER COPPER	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn85Pb15)	TIN LEAD
Terminal form	GULL WING	BALL	GULL WING	BALL	GULL WING	GULL WING
Terminal pitch	0.5 mm	1 mm	0.5 mm	1 mm	0.5 mm	0.5 mm
Terminal location	QUAD	BOTTOM	QUAD	BOTTOM	QUAD	QUAD
Maximum time at peak reflow temperature	20	30	20	20	20	20
width	20 mm	13 mm	20 mm	13 mm	20 mm	20 mm
ECCN code	-	EAR99	-	EAR99	EAR99	EAR99

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