Enhanced
Features
Memory Systems Inc.
DM512K32ST/DM512K36ST
512Kb x 32/512Kb x 36 EDRAM SIMM
Product Specification
Architecture
The DM512K36ST
achieves 512K x 36 density by
Actives Pages (Multibank Cache)
mounting five 512K x 8
s
Fast DRAM Array for 30ns Access to Any New Page
s
Write Posting Register for 12ns Random Writes and Burst Writes
EDRAMs, packaged in 44-pin
Within a Page (Hit or Miss)
plastic TSOP-II packages, on
s
1KByte Wide DRAM to SRAM Bus for 56.8 Gigabytes/Sec Cache Fill
a multi-layer substrate. Four
s
On-chip Cache Hit/Miss Comparators Maintain Cache Coherency
2203 devices and one
on Writes
DM2213 device provide data
s
Hidden Precharge and Refresh Cycles
and parity storage. The
s
Extended 64ms Refresh Period for Low Standby Power
DM512K32 contains four
s
Standard CMOS/TTL Compatible I/O Levels and +5 Volt Supply
2203 devices for data only.
s
Compatibility with JEDEC 512K x 32/36 DRAM SIMM Configuration
The EDRAM memory
Allows Performance Upgrade in System
module architecture is very
s
Industrial Temperature Range Option
similar to a standard 2MB
DRAM module with the
Description
addition of an integrated
The Enhanced Memory Systems 2MB EDRAM SIMM module
cache and on-chip control which allows it to operate much like a
provides a single memory module solution for the main memory or
page mode or static column DRAM.
local memory of fast embedded control, DSP, and other high
The EDRAM’s SRAM cache is integrated into the DRAM array as
performance systems. Due to its fast 12ns cache row register, the
tightly coupled row registers. The 512K x 32/36 EDRAM SIMM has a
EDRAM memory module supports zero-wait-state burst read
total of four independent DRAM memory banks each with its own 256
operations at up to 50MHz bus rates in a non-interleave configuration x 32/36 SRAM row register. Memory reads always occur from the
and 100MHz bus rates with a two-way interleave configuration.
cache row register of one of these banks as specified by row address
On-chip write posting and fast page mode operation supports
bits A
8
and A
9
(bank select). When the internal comparator detects
12ns write and burst write operations. On a cache miss, the fast
DRAM array reloads the entire 1KByte cache over a 1KByte-wide bus that the row address matches the last row read from any of the four
DRAM banks (page hit), the SRAM is accessed and data is available
in 18ns for an effective bandwidth of 56.8 Gbytes/sec. This means
on the output pins in 12ns from column address input. Subsequent
very low latency and fewer wait states on a cache miss than a non-
integrated cache/DRAM solution. The JEDEC compatible 72-bit SIMM reads within the page (burst reads or random reads) can continue at
12ns cycle time. When the row address does not match the last row
configuration allows a single memory controller to be designed to
support either JEDEC slow DRAMs or high speed EDRAMs to provide read from any of the four DRAM banks (page miss), the new DRAM
row is accessed and loaded into the appropriate SRAM row register
a simple upgrade path to higher system performance.
and data is available on the output pins
all within 30ns from row enable.
Functional Diagram
Subsequent reads within the page (burst
reads or random reads) can continue at
/CAL
Column
12ns cycle time.
A -A
Address
Latch
Column Decoder
Since reads occur from the SRAM
4 - 256 X 36 Cache Pages
cache, the DRAM precharge can occur
(Row Registers)
4 - 9 Bit
during burst reads. This eliminates the
Comparators
Sense Amps
precharge time delay suffered by other
/G
& Column Write Select
A -A
I/O
DRAMs and SDRAMs when accessing a
4 - Last Row
Control
Read Address
DQ
and
new page. The EDRAM has an independent
Latches
Data
Latches
on-chip refresh counter and dedicated
/S
refresh control pin to allow the DRAM array
Memory
Row
/WE
Array
Address
(2Mbyte + Parity)
Latch
to be refreshed concurrently with cache
read operations (hidden refresh).
During EDRAM read accesses, data
V
C
A -A
can be accessed in either static column
V
/F
Row Adress
s
4KByte SRAM Cache Memory for 12ns Random Reads Within Four
0-3, P
0
7
0
10
0-35
Row Decoder
CC
0
9
1-5
SS
W/R
/RE
0,2
and
Refresh
Control
Refresh
Counter
The information contained herein is subject to change without notice. Enhanced reserves the
right to change or discontinue this product without notice.
© 1996 Enhanced Memory Sytems Inc
, 1850 Ramtron Drive, Colorado Springs, CO
80921
Telephone
(800) 545-DRAM;
Fax
(719) 488-9095; http://www.csn.net/ramtron/enhanced 38-2113-000
or page mode depending upon the operation of the /CAL input. If
/CAL is held high, new data is accessed with each new column
address (static column mode). If /CAL is brought low during a
read access, the column address is latched and new data will not
be accessed until both the column address is changed and /CAL is
brought high (page mode). A dedicated output enable (/G) with
5ns access time allows high speed two-way interleave without an
external multiplexer.
Memory writes are posted to the input data latch and directed
to the DRAM array. During a write hit, the on-chip address
comparator activates a parallel write path to the SRAM cache to
maintain coherency. Random or page mode writes can be posted
5ns after column address and data are available. The EDRAM
allows 12ns page mode cycle time for both write hits and write
misses. Memory writes do not affect the contents of the cache row
register except during a cache hit. Since the DRAM array can be
written to at SRAM speeds, there is no need for complex writeback
schemes.
By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior performance over standard slow 4Mb DRAMs.
By eliminating the need for SRAMs and cache controllers, system
cost, board space, and power can all be reduced.
Functional Description
The EDRAM is designed to provide optimum memory
performance with high speed microprocessors. As a result, it is
possible to perform simultaneous operations to the DRAM and
SRAM cache sections of the EDRAM. This feature allows the EDRAM
to hide precharge and refresh operation during reads and
maximize hit rate by maintaining page cache contents during write
operations even if data is written to another memory page. These
capabilities, in conjunction with the faster basic DRAM and cache
speeds of the EDRAM, minimize processor wait states.
EDRAM Basic Operating Modes
The EDRAM operating modes are specified in the table to
follow.
Hit and Miss Terminology
In this datasheet, “hit” and “miss” always refer to a hit or miss
to any of the four pages of data contained in the SRAM cache row
Four Bank Cache Architecture
Bank 3
Bank 2
Bank 1
Bank 0
Row Address Latch
Last
Row
Read
Address
Latch
+ 9-Bit
Compare
RA
0-10
Column Address Latch
CA
0-7
512K Byte
Array
512K Byte
Array
512K Byte
Array
512K Byte
Array
D
0-35
A
0-10
Data-In
Latch
256 x 36
Cache
Bank 0
CA
0-7
256 x 36
Cache
Bank 1
256 x 36
Cache
Bank 2
256 x 36
Cache
Bank 3
(0,0)
RA
8
, RA
9
(0,1)
(1,0)
(1,1)
1 of 4 Selector
CAL
0-3, P
Data-Out
Latch
G
S
Q
0-35
1-40
registers. There are four cache row registers, one for each of the
four banks of DRAM. These registers are specified by the bank
select row address bits A
8
and A
9
. The contents of these cache row
registers is always equal to the last row that was read from each of
the four internal DRAM banks (as modified by any write hit data).
DRAM Read Hit
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
last row read address latch for the bank specified by row address
bits A
8-9
(LRR: a 9-bit row address latch for each internal DRAM
bank which is reloaded on each /RE active read miss cycle). If the
row address matches the LRR, the requested data is already in the
SRAM cache and no DRAM memory reference is initiated. The data
specified by the row and column address is available at the output
pins at the greater of times t
AC
or t
GQV
. Since no DRAM activity is
initiated, /RE can be brought high after time t
RE1
, and a shorter
precharge time, t
RP1
, is required. Additional locations within the
currently active page may be accessed concurrently with precharge
by providing new column addresses to the multiplex address
inputs. New data is available at the output at time t
AC
after each
column address change in static column mode. During any read
cycle, it is possible to operate in either static column mode with
/CAL=high or page mode with /CAL clocked to latch the column
address. In page mode, data valid time is determined by either t
AC
or t
CQV
.
column addresses to the multiplex address inputs. New data is
available at the output at time t
AC
after each column address change
in static column mode. During any read cycle, it is possible to
operate in either static column mode with /CAL=high or page
mode with /CAL clocked to latch the column address. In page
mode, data valid time is determined by either t
AC
or t
CQV
.
DRAM Write Hit
A DRAM write request is initiated by clocking /RE while W/R,
/WE, and /F are high. The EDRAM will compare the new row
address to the LRR address latch for the bank specified by row
address bits A
8-9
(LRR: a 9-bit row address latch for each internal
DRAM bank which is reloaded on each /RE active read miss cycle).
If the row address matches the LRR, the EDRAM will write data to
both the DRAM page in the appropriate bank and its corresponding
SRAM cache simultaneously to maintain coherency. The write
address and data are posted to the DRAM as soon as the column
address is latched by bringing /CAL low and the write data is
latched by bringing /WE low (both /CAL and /WE must be high
when initiating the write cycle with the falling edge of /RE). The
write address and data can be latched very quickly after the fall of
/RE (t
RAH
+ t
ASC
for the column address and t
DS
for the data).
During a write burst sequence, the second write data can be posted
at time t
RSW
after /RE. Subsequent writes within a page can occur
with write cycle time t
PC
. With /G enabled and /WE disabled, read
operations may be performed while /RE is activated in write hit
mode. This allows read-modify-write, write-verify, or random read-
DRAM Read Miss
A DRAM read request is initiated by clocking /RE with W/R low write sequences within the page with 12ns cycle times. At the end
and /F high. The EDRAM will compare the new row address to the of any write sequence (after /CAL and /WE are brought high and t
RE
is satisfied), /RE can be brought high to precharge the memory.
LRR address latch for the bank specified by row address bits A
8-9
Cache reads can be performed concurrently with precharge (see
(LRR: a 9-bit row address latch for each internal DRAM bank
“/RE Inactive Operation”). When /RE is inactive, the cache reads
which is reloaded on each /RE active read miss cycle). If the row
address does not match the LRR, the requested data is not in SRAM will occur from the page accessed during the last /RE active read
cycle. During write sequences, a write operation is not performed
cache and a new row is fetched from the DRAM. The EDRAM will
unless both /CAL and /WE are low. As a result, the /CAL input can
load the new row data into the SRAM cache and update the LRR
be used as a byte write select in multi-chip systems.
latch. The data at the specified column address is available at the
DRAM Write Miss
output pins at the greater of times t
RAC
, t
AC
, and t
GQV
. /RE may be
A DRAM write request is initiated by clocking /RE while W/R,
brought high after time t
RE
since the new row data is safely latched
/WE, and /F are high. The EDRAM will compare the new row
into SRAM cache. This allows the EDRAM to precharge the DRAM
array while data is accessed from SRAM cache. Additional locations address to the LRR address latch for the bank specified for row
within the currently active page may be accessed by providing new address bits A
8-9
(LRR: a 9-bit row address latch for each internal
EDRAM Basic Operating Modes
Function
Read Hit
Read Miss
Write Hit
Write Miss
Internal Refresh
Low Power Standby
Unallowed Mode
/S
L
L
L
L
X
H
H
/RE
↓
↓
↓
↓
↓
H
L
W/R
L
L
H
H
X
X
X
/F
H
H
H
H
L
X
H
A
0-10
Row = LRR
Row
≠
LRR
Row = LRR
Row
≠
LRR
X
X
X
Comment
No DRAM Reference, Data in Cache
DRAM Row to Cache
Write to DRAM and Cache, Reads Enabled
Write to DRAM, Cache Not Updated, Reads Disabled
Cache Reads Enabled
Standby Current
H = High; L = Low; X = Don’t Care;
↓
= High-to-Low Transition; LRR = Last Row Read
1-41
DRAM bank which is reloaded on each /RE active read miss
cycle). If the row address does not match any of the LRRs, the
EDRAM will write data to the DRAM page in the appropriate bank
and the contents of the current cache is not modified. The write
address and data are posted to the DRAM as soon as the column
address is latched by bringing /CAL low and the write data is
latched by bringing /WE low (both /CAL and /WE must be high
when initiating the write cycle with the falling edge of /RE). The
write address and data can be latched very quickly after the fall of
/RE (t
RAH
+ t
ASC
for the column address and t
DS
for the data).
During a write burst sequence, the second write data can be
posted at time t
RSW
after /RE. Subsequent writes within a page can
occur with write cycle time t
PC
. During a write miss sequence
cache reads are inhibited and the output buffers are disabled
(independently of /G) until time t
WRR
after /RE goes high. At the
end of a write sequence (after /CAL and /WE are brought high and
t
RE
is satisfied), /RE can be brought high to precharge the memory.
Cache reads can be performed concurrently with the precharge
(see “/RE Inactive Operation”). When /RE is inactive, the cache
reads will occur from the page accessed during the last /RE active
read cycle. During write sequences, a write operation is not
performed unless both /CAL and /WE are low. As a result, /CAL can
be used as a byte write select in multi-chip systems.
removed and write data can be placed on the databus. The mask
is only specified on the /RE transition. During page mode write
operations, the same mask is used for all write operations.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle. /F cycles are the
only active cycles where /S can be disabled.
/RE Only Refresh Operation
Although /F refresh using the internal refresh counter is the
recommended method of EDRAM refresh, it is possible to perform
an /RE only refresh using an externally supplied row address. /RE
refresh is performed by executing a
write cycle
(W/R and /F are
high) where /CAL is not clocked. This is necessary so that the
current cache contents and LRR are not modified by the refresh
operation. All combinations of addresses A
0-9
must be sequenced
every 64ms refresh period. A
10
does not need to be cycled. Read
refresh cycles are not allowed because a DRAM refresh cycle does
not occur when a read refresh address matches the LRR address
latch.
Low Power Mode
The EDRAM enters its low power mode when /S is high. In
this mode, the internal DRAM circuitry is powered down to reduce
standby current.
Initialization Cycles
A minimum of eight /RE active initialization cycles (read,
write, or refresh) are required before normal operation is
guaranteed. Following these start-up cycles, two read cycles to
different row addresses must be performed for each of the four
internal banks of DRAM to initialize the internal cache logic. Row
address bits A
8
and A
9
. define the four internal DRAM banks.
Unallowed Mode
Read, write, or /RE only refresh operations must not be
initiated to unselected memory banks by clocking /RE when /S is
high.
Reduced Pin Count Operation
It is possible to simplify the interface to the 2MByte SIMM to
reduce the number of control lines. /RE
0
and /RE
2
could be tied
together externally to provide a single row enable. W/R and /G can
be tied together if reads are not performed during write hit cycles.
This external wiring simplifies the interface without any
performance impact.
/RE Inactive Operation
Data may be read from the SRAM cache without clocking /RE.
This capability allows the EDRAM to perform cache read
operations during precharge and refresh cycles to minimize wait
states. It is only necessary to select /S and /G and provide the
appropriate column address to read data as shown in the table
below. In this mode of operation, the cache reads will occur from
the page accessed during the last /RE active read cycle. To perform
a cache read in static column mode, /CAL is held high, and the
cache contents at the specified column address will be valid at
time t
AC
after address is stable. To perform a cache read in page
mode, /CAL is clocked to latch the column address and data.
This option is desirable when the external control logic is
capable of fast hit/miss comparison. In this case, the controller
can avoid the time required to perform row/column multiplexing
on hit cycles.
Function
Cache Read (Static Column)
Cache Read (Page Mode)
/S
L
L
/G
L
L
/CAL
H
¤
A
0-7
Column Address
Column Address
H = High; L = Low; X = Don’t Care;
¤
= Transitioning
Write-Per-Bit Operation
The DM512K36ST SIMM provides a write-per-bit capability to
selectively modify individual parity bits (DQ
8, 17, 26, 35
) for byte
write operations. The parity device (DM2213) is selected via
/CAL
P
. Byte write selection to non-parity bits is accomplished via
CAL
0-3
. The bits to be written are determined by a bit mask data
word which is placed on the parity I/O data pins prior to clocking
/RE. The logic one bits in the mask data select the bits to be
written. As soon as the mask is latched by /RE, the mask data is
Pin Descriptions
/RE
0,2
— Row Enable
These inputs are used to initiate DRAM read and write
operations and latch a row address and the states of W/R and /F. It
is not necessary to clock /RE to read data from the EDRAM SRAM
row registers. On read operations, /RE can be brought high as
soon as data is loaded into cache to allow early precharge.
1-42
Interconnect Diagram
Edge
Connecter
J1
2
4
6
8
20
22
24
26
36
49
51
53
55
57
61
63
65
37
3
5
7
9
21
23
25
27
35
50
52
54
56
58
60
62
64
38
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
+5V
100KΩ
R1*
R2*
R3*
R4*
+5V
4
6
7
9
13
15
16
18
4
6
7
9
13
15
16
18
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
4
6
7
9
13
15
16
18
U5
Byte 4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
4
6
7
9
13
15
16
18
U3
Parity*
VCC
VCC
VCC
VCC
VCC
VCC
1
5
11
17
22
31
3
8
14
19
23
34
44
4
6
7
9
13
15
16
18
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U4
Byte 3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U2
Byte 2
48
47
68
69
67
W/R
/WE
/F
/S
/G
QLE
/CAL
32
32
40
43
41
42
46
44
34
/CAL0
/CAL1
/CAL2
/CAL3
/CALP
/RE0
/RE2
/CAL0
/CAL1
/CAL2
/CAL3
/CALP
/RE0
/RE2
+5V
10
11
30
59
66
1
29
39
71
72
70
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
PD
C1
C2
C3
33
/RE
C4
C5
*DM2213 and R
1-4
are not present on the DM512K32ST.
1-43
33
43
26
2
42
12
10
24
W/R
/WE
/F
/S
/G
QLE
/HIT
DM2203T
512K x 8
DM2203T
512K x 8
/CAL
/RE
32
/CAL
/CAL
/RE
EDRAM
32
33
/RE
EDRAM
32
33
33
12
13
14
15
16
17
18
28
31
32
19
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
27
28
29
30
35
36
37
38
39
40
41
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
U1
Byte 1
DM2213T
512K x 8
DM2203T
512K x 8
EDRAM
/CAL
DM2203T
512K x 8
EDRAM
/RE
EDRAM
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FPGA/CPLD
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