512Kx8, 55 - 120ns, DLCC
30A142-00
B
4 Megabit CMOS SRAM
DPS512E8MGG
DESCRIPTION:
The DPS512E8MGG is a monolithic 512K x 8 Static
Random Access Memory (SRAM) fabricated using
CMOS technology. It is designed for use in high
density, low power applications. All pins are TTL
compatible and a single +5 Volt power supply is
required.
The DPS512E8MGG has very low standby power
requirements, making is suitable for applications
needing battery backup.
Each device is packaged in a 32-pin, hermetically
sealed LCC, making the device suitable for
commercial, industrial and military applications.
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
•
Organizations Available: 512K x 8
•
Access Times: 55, 70, 85, 100, 120ns (max.)
•
Fully Static Operation - No clock or refresh
required
•
Single +5V Power Supply, ±10% Tolerance
•
TTL Compatible
•
Common Data Inputs and Outputs
•
Low Data Retention Voltage:
2.0V min.
•
Package Available: 32- pad Inline LCC
PIN-OUT DIAGRAM
PIN NAMES
A0 - A18
I/O0 - I/O7
CE
WE
OE
V
DD
V
SS
Address Inputs
Data Input/Output
Low Chip Enable
Write Enable
Output Enable
Power (+5V)
Ground
30A142-00
REV. B
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
DPS512E8MGG
RECOMMENDED OPERATING RANGE
3
Dense-Pac Microsystems, Inc.
TRUTH TABLE
Mode
Not Selected
D
OUT
Disable
Read
Write
H = HIGH
Symbol
Characteristic
Min. Typ.
Max. Unit
V
DD
Supply Voltage
4.5 5.0
5.5
V
V
IH
Input HIGH Voltage 2.2
V
DD
+0.3 V
V
IL
Input LOW Voltage -0.5
2
0.8
V
M/B -55 +25 +125
Operating
o
T
A
I
-40 +25
+85
C
Temperature
C
0 +25
+70
CE
H
L
L
L
WE
X
H
H
L
L = LOW
OE
X
H
L
X
Supply
I/O Pin Current
High-Z Standby
High-Z Active
D
OUT
Active
D
IN
Active
X = Don’t Care
3
ABSOLUTE MAXIMUM RATINGS
Symbol
T
STC
T
BIAS
V
DD
V
I/O
CAPACITANCE
4
:
T
A
= 25°C, F = 1.0MHz
Symbol
C
ADR
C
CE
C
WE
C
OE
C
I/O
Parameter
Address Input
Chip Enable
Write Enable
Output Enable
Data Input/Output
Max.
10
10
10
10
12
Unit
Condition
Parameter
Value
Unit
Storage Temperature
-65 to +150
°C
Temperature Under Bias
-55 to +125
°C
1
Supply Voltage
-0.5 to +7.0
°C
1
Input/Output Voltage
-0.5 to V
DD
+0.5 V
DC OUTPUT CHARACTERISTICS
pF
V
IN2
=
0V
Symbol
Parameter
V
OH
HIGH Voltage
V
OL
LOW Voltage
Conditions Min. Max. Unit
I
OH
= -1.0mA 2.4
V
I
OL
=2.1mA
0.4
V
DC OPERATING CHARACTERISTICS:
Over operating ranges
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
I
DR3
I
DR2
V
OL
V
OH
Characteristics
Input
Leakage Current
Output
Leakage Current
Operating
Supply Current
Full Standby
Supply Current
Standby Current (TTL)
Data Retention
Supply Current (3.0V)
Data Retention
Supply Current (2.0V)
Output Low Voltage
Output High Voltage
Test Conditions
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD
,
CE or OE = V
IH
, or WE = V
IL
Cycle=min., Duty=100%
I
OUT
= 0mA
V
IN
≥
V
DD
-0.2V or
V
IN
≤
V
SS
+0.2V
CE = V
IH
V
DR
= 3V, CE
≥
V
DR
-0.2V
V
DR
= 2V, CE
≥
V
DR
-0.2V
I
OUT
= 2.1mA
I
OUT
= -1.0mA
2.4
C
Min.
Max.
Min.
I
Max.
Min.
M/B
Max.
Unit
µA
µA
mA
mA
mA
µA
µA
V
V
-1
-1
+1
+1
90
200
3
200
180
0.4
-1
-1
+1
+1
90
300
5
250
225
0.4
-1
-1
+1
+1
100
600
5
500
450
0.4
2.4
2.4
† Typical measurements made at +25
o
C, Cycle = min., V
DD
= 5.0V.
Data Retention AC Characteristics
Symbol
V
DR
V
CDR
t
R
Parameter
V
DD
for Data Retention
Chip Disable to
Data Retention Time
Operation Recovery Time
Test Conditions
CE
≥
V
DR
-0.2V
See Data Retention Waveform
See Data Retention Waveform
8
Min.
2.0
0
5
Typ.
-
-
-
Max.
-
-
-
Unit
V
ns
ms
2
30A142-00
REV. B
Dense-Pac Microsystems, Inc.
DPS512E8MGG
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
0V to 3.0V
5ns
1.5V
Figure 1. Output Load
* Including Probe and Jig Capacitance.
+5V
1.8KΩ
OUTPUT LOAD
Load
1
2
C
L
100pF
5pF
Parameters Measured
except t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
D
OUT
C
L
*
990Ω
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
Over operating ranges
No. Symbol
1
2
3
4
5
6
7
8
9
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
Parameter
Read Cycle Time
Address Access Time
CE to Output Valid
Output Enable to Output Valid
CE to Output in LOW-Z
4, 5
Output Enable to Output in LOW-Z
4, 5
CE to Output in HIGH-Z
4, 5
Output Enable to Output in HIGH-Z
4, 5
Output Hold from Address Change
55ns
Min.
Max.
70ns
Min.
Max.
85ns
Min.
Max.
100ns
Min.
Max.
120ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
55
55
25
10
5
0
0
10
70
70
70
35
10
5
0
0
10
85
85
85
45
10
5
0
0
10
100
100
100
50
10
5
0
0
10
120
120
120
60
10
5
0
0
10
20
20
25
25
30
30
30
30
35
35
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE
6, 7
:
Over operating ranges
No. Symbol
10
11
12
13
14
15
16
17
18
19
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Parameter
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-Up Time **
Write Pulse Width
Write Recovery Time
Write Enable to Output in HIGH-Z
4, 5
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
55ns
Min.
Max.
70ns
Min.
Max.
85ns
Min.
Max.
100ns
Min.
Max.
120ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
45
45
0
40
0
0
25
0
5
20
70
60
60
0
50
0
0
30
0
5
25
85
70
70
0
55
0
0
35
0
5
30
100
80
80
0
60
0
0
40
0
5
30
120
90
90
0
65
0
0
45
0
5
35
** Valid for both Read and Write Cycles.
30A142-00
REV. B
3
DPS512E8MGG
Dense-Pac Microsystems, Inc.
DATA RETENTION WAVEFORM:
CE Controlled.
V
DD
4.5V
2.3V
V
DR1
CE
0V
CE
≥
V
DD
-0.2V
READ CYCLE
ADDRESS
CE
OE
DATA I/O
WRITE CYCLE 1:
CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
4
30A142-00
REV. B
Dense-Pac Microsystems, Inc.
DPS512E8MGG
WRITE CYCLE 2:
WE Controlled. OE is HIGH.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 3:
WE Controlled. OE is LOW.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
WAVEFORM KEY
Data Valid
Transition from
HIGH to LOW
Transition from
LOW to HIGH
Data Undefined
or Don’t Care
30A142-00
REV. B
5
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