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EPM570GT100I3N

Description
Flash PLD, 5.4ns, 440-Cell, CMOS, PQFP100, 16 X 16 MM, 0.50 MM PITCH, LEAD FREE, TQFP-100
CategoryProgrammable logic devices    Programmable logic   
File Size1MB,108 Pages
ManufacturerAltera (Intel)
Environmental Compliance  
Download Datasheet Parametric View All

EPM570GT100I3N Overview

Flash PLD, 5.4ns, 440-Cell, CMOS, PQFP100, 16 X 16 MM, 0.50 MM PITCH, LEAD FREE, TQFP-100

EPM570GT100I3N Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerAltera (Intel)
Parts packaging codeQFP
package instructionTFQFP, TQFP100,.63SQ
Contacts100
Reach Compliance Codecompliant
Other featuresIT CAN ALSO OPERATE AT 3.3V
In-system programmableYES
JESD-30 codeS-PQFP-G100
JESD-609 codee3
JTAG BSTYES
length14 mm
Humidity sensitivity level3
Dedicated input times
Number of I/O lines76
Number of macro cells440
Number of terminals100
organize0 DEDICATED INPUTS, 76 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeTFQFP
Encapsulate equivalent codeTQFP100,.63SQ
Package shapeSQUARE
Package formFLATPACK, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)260
power supply1.5/3.3,1.8 V
Programmable logic typeFLASH PLD
propagation delay5.4 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width14 mm
Section I. MAX II Device
Family Data Sheet
This section provides designers with the data sheet specifications for
MAX
®
II devices. The chapters contain feature definitions of the internal
architecture, Joint Test Action Group (JTAG) and in-system
programmability (ISP) information, DC operating conditions, AC timing
parameters, and ordering information for MAX II devices.
This section includes the following chapters:
Chapter 1. Introduction
Chapter 2. MAX II Architecture
Chapter 3. JTAG and In-System Programmability
Chapter 4. Hot Socketing and Power-On Reset in MAX II Devices
Chapter 5. DC and Switching Characteristics
Chapter 6. Reference and Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information
about when each chapter was updated, refer to the Chapter Revision
Dates section, which appears in the complete handbook.
Altera Corporation
Section I–1
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