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Data Sheet
November 2003
N
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n
© 2013 Rochester Electronics, LLC. All Rights Reserved 03132013
tact ou IL or www.i
c on
T ER S
-888-IN
1
®
ICM7170
FN3019.6
ICM7170
Microprocessor-Compatible,
Real-Time
Clock
The ICM7170 real time clock is a microprocessor bus
compatible peripheral, fabricated using Intersil’s silicon gate
CMOS LSl process. An 8-bit bidirectional bus is used for the
data I/O circuitry. The clock is set or read by accessing the 8
internal separately addressable and programmable counters
from
1
/
100
seconds to years. The counters are controlled by
a pulse train divided down from a crystal oscillator circuit,
and the frequency of the crystal is selectable with the
on-chip command register. An extremely stable oscillator
frequency is achieved through the use of an on-chip
regulated power supply.
The device access time (t
ACC
) of 300ns eliminates the need
for wait states or software overhead with most
microprocessors. Furthermore, an ALE (Address Latch
Enable) input is provided for interfacing to microprocessors
with a multiplexed address/data bus. With these two special
features, the ICM7170 can be easily interfaced to any
available microprocessor.
The ICM7170 generates two types of interrupts, periodic and
alarm. The periodic interrupt (100Hz, 10Hz, etc.) can be
programmed by the internal interrupt control register to
provide 6 different output signals. The alarm interrupt is set
by loading an on-chip 51-bit RAM that activates an interrupt
output through a comparator. The alarm interrupt occurs
when the real time counter and alarm RAM time are equal. A
status register is available to indicate the interrupt source.
An on-chip Power Down Detector eliminates the need for
external components to support the battery back-up
function. When a power down or power failure occurs,
internal logic switches the on-chip counters to battery back-
up operation. Read/write functions become disabled and
operation is limited to time-keeping and interrupt generation,
resulting in low power consumption.
Internal latches prevent clock roll-over during a read cycle.
Counter data is latched on the chip by reading the
100th-seconds counter and is held indefinitely until the
counter is read again, assuring a stable and reliable time
value.
Features
• 8-Bit,
µP
Bus Compatible
- Multiplexed or Direct Addressing
• Regulated Oscillator Supply Ensures Frequency Stability
and Low Power
• Time From 1/100 Seconds to 99 Years
• Software Selectable 12/24 Hour Format
• Latched Time Data Ensures No Roll Over During Read
• Full Calendar with Automatic Leap Year Correction
• On-Chip Battery Backup Switchover Circuit
• Access Time Less than 300ns
• 4 Programmable Crystal Oscillator Frequencies Over
Industrial Temperature Range
• 3 Programmable Crystal Oscillator Frequencies Over
Military Temperature Range
• On-Chip Alarm Comparator and RAM
• Interrupts from Alarm and 6 Selectable Periodic Intervals
• Standby Micro-Power Operation: 1.2µA Typical at 3.0V
and 32kHz Crystal
Applications
• Portable and Personal Computers
• Data Logging
• Industrial Control Systems
• Point Of Sale
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Part Number Information
PART NUMBER
ICM7170IPG
ICM7170IBG
ICM7170AIPG
TEMP. RANGE
(
o
C)
-40× to 85×
-40× to 85×
-40× to 85×
PACKAGE
24 Ld PDIP
24 Ld SOIC
24 Ld PDIP
PKG.
NO.
E24.6
M24.3
E24.6
M24.3
For complete Rochester ordering guide, please
-40× to 85×
page
SOIC
refer to
24 Ld
2
ICM7170AIBG
Please consult factory for specific package availability
at 32kHz.
NOTE: “A” Parts Screened to <5µA I
STBY
Rochester Electronics guarantees performance of its semiconductor products to the original OEM specifications. “Typical” values are for reference purposes
only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. Rochester Electronics reserves
the right to make changes without further notice to any specification herein.
Specification Number ICM7170_IM (IL)
CAUTION:
-
These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
REV
Page 1 of 14
1
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|
ICM7170
ICM7170
Absolute Maximum Ratings
T
A
= 25
o
C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Power Dissipation (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . .500mW
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65
o
C to 150
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . .300
o
C
Input Voltage (Any Terminal) (Note 2) . . . . V
DD
+0.3V to V
SS
-0.3V
Thermal Information
Thermal Resistance (Typical, Note 1)
PDIP Package . . . . . . . . . . . . . . . . . . .
50
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
75
N/A
Maximum Junction Temperature
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
o
C
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. Due to the SCR structure inherent in the CMOS process, connecting any terminal at voltages greater than V
DD
or less than V
SS
may cause destructive
device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same power supply be applied to the
device before its supply is established, and that in multiple supply systems, the supply to the ICM7170 be turned on first.
Electrical Specifications
PARAMETER
V
DD
Supply Range, V
DD
T
A
= -40
o
C to 85
o
C, V
DD
+5V
±10%,
V
BACKUP
V
DD
, V
SS
= 0V Unless Otherwise Specified
All I
DD
specifications include all input and output leakages (ICM7170 and ICM7170A)
TEST CONDITIONS
f
OSC
= 32kHz
f
OSC
= 1, 2, 4MHz
MIN
1.9
2.6
ICM7170
ICM7170A
-
-
-
-
-
-
2.4
-
2.4
-10
-10
2.6
1.9
INT SOURCE
Connected to V
SS
-
-
-
TYP
-
-
1.2
1.2
20
0.3
1.0
-
-
-
-
0.5
0.5
-
-
0.5
8
6
MAX
5.5
5.5
20.0
5.0
150
1.2
2.0
0.8
-
0.4
-
+10
+10
V
DD
- 1.3
V
DD
- 1.3
10
-
-
UNITS
V
V
µA
Standby Current, I
STBY(1)
f
OSC
= 32kHz
Pins 1 - 8,15 - 22 and 24 = V
DD
V
DD
= V
SS
; V
BACKUP
= V
DD
- 3.0V
For ICM7170A See General Notes 5
µA
Standby Current, I
STBY
(2)
Operating Supply Current, I
DD(1)
Operating Supply Current, I
DD(2)
Input Low Voltage (Except Osc.), V
IL
Input High Voltage (Except Osc.), V
IH
Output Low Voltage (Except Osc.), V
OL
Output High Voltage Except
INTERRUPT (Except Osc.), V
OH
Input Leakage Current, I
IL
Three-State Leakage Current
(D0 - D7), I
OL
(1)
Backup Battery Voltage, V
BATTERY
Backup Battery Voltage, V
BATTERY
Leakage Current INTERRUPT, I
OL
(2)
Capacitance D0 - D7, C
I/O
Capacitance A0 - A4, C
ADDRESS
f
OSC
= 4MHz Pins 1 - 8,15 - 22 and 24 = V
DD
V
DD
= V
SS
; V
BACKUP
= V
DD
- 3.0V
f
OSC
= 32kHz, Read/Write Operation at 100Hz
f
OSC
= 32kHz, Read/Write Operation at 1MHz
V
DD
= 5.0V
V
DD
= 5.0V
I
OL
= 1.6mA
I
OH
= -400µA
V
IN
= V
DD
or V
SS
V
O
= V
DD
or V
SS
f
OSC
= 1, 2, 4MHz
f
OSC
= 32kHz
V
O
= V
DD
µA
mA
mA
V
V
V
V
µA
µA
V
V
µA
pF
pF
Specification Number ICM7170_IM (IL) REV -
3
Page 4 of 14
ICM7170
ICM7170
AC Electrical Specifications
T
A
= -40
o
C to 85
o
C, V
DD
= +5V
±
10%, V
BACKUP
= V
DD
,
MIN
D0 - D7 Load Capacitance = 150pF, V
IL
= 0.4V, V
lH
= 2.8V, Unless Otherwise Specified
MAX
UNITS
PARAMETER
READ CYCLE TIMING
READ to DATA Valid, t
RD
ADDRESS Valid to DATA Valid, t
ACC
READ Cycle Time, t
CYC
Read High Time, t
RH
RD High to Bus Three-State, t
RH
ADDRESS to READ Set Up Time, t
AS
ADDRESS HOLD Time After READ, t
AR
WRITE CYCLE TIMING
ADDRESS Valid to WRITE Strobe, t
AD
ADDRESS Hold Time for WRITE, t
WA
WRITE Pulse Width, Low, t
WL
WRITE High Time, t
WH
DATA IN to WRITE Set Up Time, t
DW
DATA IN Hold Time After WRITE, t
WD
WRITE Cycle Time, t
CYC
MULTIPLEXED MODE TIMING
ALE Pulse Width, High, t
LL
ADDRESS to ALE Set Up Time, t
AL
ADDRESS Hold Time After ALE, t
LA
-
-
400
150
-
50
0
250
300
-
-
25
-
-
ns
ns
ns
ns
ns
ns
ns
50
0
100
300
100
30
400
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
50
30
30
-
-
-
ns
ns
ns
Timing Diagrams
A0 - A4, CS
t
AS
t
CYC
RD
t
RD
ADDRESS VALID, CS LOW
t
AR
D0 - D7
t
ACC
OUTPUT DATA VALID
t
RX
FIGURE 1. READ CYCLE TIMING FOR NON-MULTIPLEXED BUS (ALE = V
IH
, WR = V
IH
)
Specification Number ICM7170_IM (IL) REV -
4
Page 5 of 14
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