P4C116/P4C116L
ULTRA HIGH SPEED 2K x 8
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35 ns (Commercial)
– 12/15/20/25/35 ns (Industrial)
– 15/20/25/35 ns (Military)
Low Power Operation
Output Enable Control Function
Single 5V±10% Power Supply
Common Data I/O
Fully TTL Compatible Inputs and Outputs
Produced with PACE II Technology
TM
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP, SOIC, SOJ
– 24-Pin 600 mil DIP
– 24-Pin Solder Seal Flat Pack
– 24-Pin Rectangular LCC (300 x 400 mils)
– 28-Pin Square LCC (450 x 450 mils)
– 32-Pin Rectangular LCC (450 x 550 mils)
– 40-Pin Square LCC (480 x 480 mils)
DESCRIPTIOn
The P4C116/P4C116L are 16,384-bit ultra high-speed
static RAMs organized as 2K x 8. The CMOS memories
require no clocks or refreshing and have equal access and
cycle times. Inputs are fully TTL-compatible. The RAMs
operate from a single 5V±10% tolerance power supply.
Current drain is typically 10 µA from a 2.0V supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption.
The P4C116 is available in 24-pin 300 and 600 mil DIP,
SOJ and SOIC packages, a solder seal flatpack and 4
different LCC packages (24, 28, 32, and 40 pin).
FUnCTIOnAL BLOCk DIAgRAM
PIn COnFIgURATIOnS
DIP (C4, C12, D4, P4), SOJ (J4), SOIC (S4)
SOLDER SEAL FLAT PACK (FS-1) SIMILAR
LCC configurations at end of datasheet
Document #
SRAM110
REV C
Revised May 2009
P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS
MAxIMUM RATIngS
(1)
Sym
V
CC
V
TERM
T
A
T
BIAS
T
STG
P
T
I
OUT
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND (up to
7.0V)
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +7
-0.5 to VCC + 0.5
-55 to +125
-55 to +125
-65 to +150
1.0
50
Unit
V
V
°C
°C
°C
W
mA
RECOMMEnDED OPERATIng COnDITIOnS
grade
(2)
Commercial
Industrial
Military
Ambient Temp
0°C to 70°C
-40°C to +85°C
-55°C to +125°C
gnD
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CAPACITAnCES
(4)
Sym
C
IN
C
OUT
Parameter
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Conditions
V
IN
=0V
V
OUT
=0V
Typ
5
7
Unit
pF
pF
Input Capacitance
Output Capacitance
DC ELECTRICAL CHARACTERISTICS
Sym Parameter
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
(Over Recommended Operating Temperature & Supply Voltage)
(2)
Test Conditions
P4C116
Min
2.2
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
Max
V
CC
+ 0.5
0.8
V
CC
+ 0.5
0.2
-1.2
0.4
2.4
MIL
IND/COM
MIL
IND/COM
MIL
IND/COM
MIL
IND/COM
P4C116L
Min
2.2
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
Max
V
CC
+ 0.5
0.8
V
CC
+ 0.5
0.2
-1.2
0.4
2.4
Unit
V
V
V
V
V
V
V
Input Clamp Diode Voltage V
CC
= Min, I
IN
= -18 mA
Output Low Voltage (TTL
Load)
Output High Voltage (TTL
Load)
Input Leakage Current
I
OL
= +8 mA, V
CC
= Min
I
OH
= - 4 mA, V
CC
= Min
V
CC
= Max,
V
IN
= GND to V
CC
-10
-5
-10
-5
—
—
—
—
+10
+5
+10
+5
30
20
15
10
-5
N/A
-5
N/A
—
—
—
—
+5
µA
N/A
+5
µA
N/A
20
mA
N/A
1
mA
N/A
I
LI
I
LO
Output Leakage Current
V
CC
= Max,
CE
= V
IH
,
V
OUT
= GND to V
CC
I
SB
Standby Power Supply
Current (TTL Input Levels)
CE
≥ V
IH
, V
CC
= Max, f = Max,
Outputs Open
CE
≥ V
HC
, V
CC
= Max, f = 0,
Outputs Open
V
IN
≤ V
LC
or V
IN
≥ V
HC
I
SB1
Standby Power Supply
Current (CMOS Input
Levels)
N/A = Not applicable
Document #
SRAM110
REV C
Page 2
P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS
DATA RETEnTIOn CHARACTERISTICS (P4C116L Military Temperature Only)
Sym
V
DR
I
CCDR
t
CDR
t
R†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
CE
≥ V
CC
-0.2V,
V
IN
≥ V
CC
-0.2V
or V
IN
≤ 0.2V
0
t
RC§
Test Conditions
Min
2.0
10
15
600
900
Typ* V
CC
=
2.0V
3.0V
Max V
CC
=
2.0V
3.0V
Unit
V
µA
ns
ns
* T
A
= +25°C
§ t
RC
= Read Cycle Time
† This Parameter is guaranteed but not tested
DATA RETEnTIOn WAVEFORM
POWER DISSIPATIOn CHARACTERISTICS VS. SPEED
Sym
I
CC
Parameter
Dynamic Operating Current*
Temperature Range
Commercial
Industrial
Military
-10
180
N/A
N/A
-12
170
180
N/A
-15
160
170
170
-20
155
160
160
-25
150
155
155
-35
140
150
150
Unit
mA
mA
mA
* V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
,
OE
= V
IH
.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable Low to Data Valid
Output Enable Low to Low Z
Output Enable High to High Z
Chip Enable to Power Up Time
Chip Disable to Power Down
0
10
0
6
0
12
2
2
5
6
0
7
0
15
-10
Min
10
10
10
2
2
6
8
0
8
0
20
Max
-12
Min
12
12
12
2
2
7
10
0
9
0
20
Max
-15
Min
15
15
15
2
2
8
10
0
12
0
25
Max
-20
Min
20
20
20
2
3
10
15
0
15
Max
-25
Min
25
25
25
2
3
15
20
Max
-35
Min
35
35
35
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #
SRAM110
REV C
Page 3
P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS
TIMIng WAVEFORM OF READ CYCLE nO. 1 (OE COnTROLLED)
(5)
TIMIng WAVEFORM OF READ CYCLE nO. 2 (ADDRESS COnTROLLED)
(5,6)
TIMIng WAVEFORM OF READ CYCLE nO. 3 (CE COnTROLLED)
notes:
1. Stresses greater than those listed under MAxIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAxIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
WE
is HIGH for READ cycle.
6.
CE
is LOW and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
transition
LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM110
REV C
Page 4
P4C116/P4C116L - ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym Parameter
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Write Cycle Time
Chip Enable Time to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Address Hold Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
0
-10
Min
10
8
8
0
8
0
7
0
6
0
Max
12
10
10
0
10
0
8
0
7
0
-12
Min
Max
15
12
12
0
12
0
10
0
8
0
-15
Min
Max
20
15
15
0
15
0
12
0
10
0
-20
Min
Max
25
18
18
0
18
0
15
0
15
0
-25
Min
Max
35
25
25
0
20
0
20
0
15
-35
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMIng WAVEFORM OF WRITE CYCLE nO. 1 (WE COnTROLLED)
(10,11)
Notes:
10.
CE
and
WE
must be LOW for WRITE cycle.
11.
OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
12. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM110
REV C
Page 5
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