P ro du c t Br ie f
Fusion Family of Mixed-Signal Flash FPGAs
With Optional Soft ARM
®
Support
Features and Benefits
High Performance Reprogrammable
Flash Technology
•
•
•
•
•
Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process
Nonvolatile, Retains Program When Powered-Off
Live at Power-Up (LAPU) Single-Chip Solution
350 MHz System Performance
User Flash Memory 2 Mbit to 8 Mbit in Density
– Configurable 8-, 16-, or 32-Bit Data Path
– Runtime Read and Write During with 10 ns Access Read-
Ahead Mode
1 kbit of Additional FlashROM
Up to 600 ksps in 8-, 10-, and 12-Bit Resolution Modes with
Internal 2.56 V or External Reference Voltage
ADC: Up to 30 Scalable Analog Input Channels
High Voltage Direct-Connect Input Tolerance ±12 V
Current Monitor and Temperature Monitor
Up to 10 MOSFET Gate Driver Outputs
– Interfaces to P- or N-Channel Power MOSFETs with
Programmable 1, 3, 10, 30 µA and 25 mA Drive Strengths
External 32 kHz to 20 MHz Crystals Oscillator or Internal
100 MHz RC Oscillator (accurate to 1%)
Programmable Real-Time Counter (RTC)
6 Clock Conditioning Circuits (CCCs) with 1 or 2 integrated PLLs
– Phase Shift, Multiply/Divide, and Delay Capabilities
•
•
•
•
•
•
•
–
®
Frequency Range: Input (1.5–350 MHz), Output (0.75–
350 MHz)
Low Power Consumption
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
Sleep and Standby Low Power Modes
Secure ISP with 128-Bit AES Via JTAG
FlashLock to Secure FPGA Contents
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages – Up to 5 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V /
1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS 2.5 V / 5.0 V
Input
Differential I/O Standards: LVPECL and LVDS
– Built-In I/O Registers
– 700 Mbps DDR Operation
Hot-Swappable I/Os
Programmable Output Slew Rate, Drive Strength, and Weak
Pull-Up/Down
Pin-Compatible Packages Across the Fusion Family
Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (x1, x2, x4, x9,
and x18 organizations available)
True Dual-Port SRAM (except x18)
Programmable Embedded FIFO Control Logic
CoreMP7S and CoreMP7Sd (with debug)
AFS250
250,000
6,144
AFS600
M7AFS600
90,000
2,304
600,000
13,824
7,500
5,237
Yes
1
18
1
2M
1k
1
In-System Programming (ISP) and Security
Advanced Digital I/O
Embedded Flash Memory
•
•
•
•
•
•
Integrated A/D Converter (ADC) and Analog I/O
•
•
•
•
•
•
•
•
SRAMs and FIFOs
On-Chip Clocking Support
•
•
•
Soft ARM7™ Core Support in M7 Fusion Devices
Table 1 •
Fusion Family
AFS090
System Gates
Tiles (D-Flip-Flops)
Usable Tiles with
Secure (AES) ISP
PLLs
Globals
Flash Memory Blocks (2 Mbits)
Flash Memory Bits
CoreMP7S
1
Yes
1
18
1
2M
1k
8
36
6
18
6
4
114
24
AFS1500
M7AFS1500
1,500,000
38,400
32,000
29,878
Yes
2
18
4
8M
1k
56
252
10
30
10
5
278
40
Fusion Devices
ARM7-Ready Fusion Devices
General
Information
Usable Tiles with CoreMP7Sd
1
Yes
2
18
2
4M
1k
20
90
10
30
10
5
172
40
Memory
FlashROM Bits
Usable RAM Blocks (4,608 bits)
Usable RAM kbits
Analog Quads
Analog Input Channels
Gate Driver Outputs
I/O Banks (+ JTAG)
Maximum Digital I/Os
2
Analog I/Os
6
27
5
15
5
4
73
20
Analog and I/Os
Notes:
1. Refer to the
CoreMP7
datasheet for more information.
2. Some debug tools require 10 digital I/Os for external connection.
February 2006
© 2006 Actel Corporation
1
Fusion Family of Mixed-Signal Flash FPGAs
Package I/Os: Digital/Analog
Fusion Devices
ARM7-Ready Devices
QN108
QN180
PQ208
FG256
FG484
FG676
36/14
48/20
–
73/20
–
–
62/24
93/24
114/24
–
–
AFS090
AFS250
AFS600
M7AFS600
–
–
95/40
119/40
172/40
–
AFS1500
M7AFS1500
–
–
–
119/40
228/40
278/40
Product Ordering Codes
M7AFS600
_
1
FG
256
G
I
Application (Ambient Temperature Range)
Blank = Commercial (0 to +70˚C)
I = Industrial (–40 to +85˚C)
PP = Pre-Production
ES = Engineering Silicon (Room Temperature Only)
Lead-Free Packaging Options
Blank = Standard Packaging
G = RoHS-Compliant (Green) Packaging
Package Lead Count
Package Type
QN = Quad Flat No Lead (0.5 mm pitch)
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
F = 20% Slower than Standard
Blank = Standard
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Part Number
Fusion Devices
AFS090 = 90,000 System Gates
AFS250 = 250,000 System Gates
AFS600 = 600,000 System Gates
AFS1500 = 1,500,000 System Gates
ARM7-Ready Fusion Devices
M7AFS600 = 600,000 System Gates
M7AFS1500 = 1,500,000 System Gates
Note:
DC and switching characteristics for –F speed grade targets based only on simulation. The characteristics provided for –F speed
grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future
revisions of this document. The –F speed grade is only supported in commercial temperature range.
P rod u c t B ri ef
3
Fusion Family of Mixed-Signal Flash FPGAs
Introduction and Overview
Introduction
The Actel Fusion™ Programmable System Chip (PSC)
satisfies the demand from system architects for a device
that simplifies design and unleashes their creativity. As
the world’s first mixed-signal FPGA family, Fusion
integrates mixed-signal analog, Flash memory, and FPGA
fabric in a monolithic PSC. Actel Fusion devices enable
designers to quickly move from concept to completed
design, and then deliver feature-rich systems to market.
This new technology takes advantage of the unique
properties of Actel Flash-based FPGAs, including a high-
isolation, triple-well process, and the ability to support
high-voltage transistors to meet the demanding
requirements of mixed-signal system design.
Actel Fusion PSCs bring the benefits of programmable
logic to many application areas, including power
management, smart battery charging, clock generation
and management, and motor control. Until now, these
applications have only been implemented with costly
and space-consuming discrete analog components or
mixed-signal ASIC solutions. Actel Fusion PSCs present
new capabilities for system development by allowing
designers to integrate a wide range of functionality into
a single device, while at the same time offering the
flexibility of upgrades late in the manufacturing process
or after the device is in the field. Actel Fusion devices
provide an excellent alternative to costly and time-
consuming mixed-signal ASIC designs. In addition, when
used in conjunction with the Actel 8051-based or ARM-
based soft MCU core, the Actel Fusion technology
represents the definitive PSC platform.
Flash-based Fusion devices are live at power-up. As soon
as system power is applied and within normal operating
specifications, Fusion devices are working. Fusion devices
have a 128-bit Flash-based lock and industry-leading AES
decryption, used to secure programmed intellectual
property (IP) and configuration data. Actel Fusion
devices are the most comprehensive single-chip analog
and digital programmable logic solution available today.
To support this new ground-breaking technology, Actel
has developed a series of major tool innovations to help
maximize designer productivity. Implemented as
extensions to the popular Actel Libero
®
Integrated
Design Environment (IDE), these new tools will allow
designers to easily instantiate and configure peripherals
within a design, establish links between peripherals,
create or import building blocks or reference designs,
and perform hardware verification. This tools suite will
also add a comprehensive hardware/software debug
capability as well as a suite of utilities to simplify
development of embedded soft processor-based
solutions.
General Description
The Actel Fusion family, based on the highly successful
ProASIC
®
3 and ProASIC3E Flash FPGA architecture, has
been designed as a high-performance, programmable,
mixed-signal platform. By combining an advanced Flash
FPGA core with Flash memory blocks and analog
peripherals, Fusion devices dramatically simplify system
design, and as a result, dramatically reduce overall
system cost and board space.
The state-of-the-art Flash memory technology offers
high-density integrated Flash memory blocks, enabling
savings in cost, power, and board area relative to
external Flash solutions, while providing increased
flexibility and performance. The Flash memory blocks
and integrated analog peripherals enable true mixed-
mode programmable logic designs. Two examples
include using an on-chip soft processor to implement a
fully functional Flash MCU, or using high-speed FPGA
logic to offer system and power supervisory capabilities.
Live at power-up and capable of operating from a single
3.3 V supply, the Fusion family is ideally suited for system
management and control applications.
The devices in the Fusion family are categorized by FPGA
core density. Each family member supports many
peripherals, including Flash memory blocks, analog to
digital converter (ADC), high-drive outputs, both RC and
crystal oscillators, and real-time counter (RTC). This
provides the user with a high level of flexibility and
integration to support a wide variety of mixed-signal
applications. The Flash memory block capacity ranges
from 2 Mbits to 8 Mbits. The integrated 12-bit ADC
supports up to 30 independently configurable input
channels. The on-chip crystal and RC oscillators work in
conjunction with the integrated Phase-Locked Loops
(PLLs) to provide clocking support to the FPGA array and
on-chip resources. In addition to supporting typical RTC
uses such as watchdog timer, the Fusion RTC can control
the on-chip voltage regulator to power down the device
(FPGA fabric, Flash memory block, and ADC), enabling a
low power sleep mode.
P rod u c t B ri ef
5
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