P r o du c t B r i e f
IGLOO
TM
Low Power Flash FPGAs with
Flash*Freeze
TM
Technology
Features and Benefits
Low Power
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5 µW Power Consumption in Flash*Freeze Mode
1.2 V or 1.5 V Core Voltage for Low Power
Supports Single-Voltage System Operation
Low Power Active Capability Enables Active FPGA
Operation with Ultra-Low Power (from 25 µW)
Flash*Freeze Technology Enables Ultra-Low Power
Consumption While Maintaining FPGA Content
Quick and Easy Way to Enter and Exit Flash*Freeze
Mode Using Flash*Freeze Pin
30 k to 1 Million System Gates
Up to 144 kbits of True Dual-Port SRAM
Up to 300 User I/Os
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
Live At Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except AGL030) via JTAG
(IEEE 1532-compliant)
FlashLock
®
to Secure FPGA Contents
Segmented, Hierarchical Routing and Clock Structure
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
Advanced I/O
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700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—Up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V/
2.5 V/1.8 V/1.5 V, 3.3 V PCI/ 3.3 V PCI-X (except
AGL030), and LVCMOS 2.5 V/5.0 V Input
Differential I/O Standards: LVPECL, LVDS, BLVDS, and
M-LVDS (AGL250 and above)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os (AGL030 only)
Programmable Output Slew Rate (except AGL030) and
Drive Strength
Weak Pull-Up/Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages Across the IGLOO Family
High Capacity
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Reprogrammable Flash Technology
Clock Conditioning Circuit (CCC) and PLL (except
AGL030)
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Six CCC Blocks, One with an Integrated PLL
Flexible Phase-Shift, Multiply/Divide, and Delay
Capabilities
Wide Input Frequency Range (1.5 MHz to 200 MHz)
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect Ratio 4,608-Bit
RAM Blocks (x1, x2, x4, x9, and x18 organizations
available)
True Dual-Port SRAM (except x18)
In-System Programming (ISP) and Security
Embedded Memory
High-Performance Routing Hierarchy
Table 1 •
IGLOO Product Family
AGL030
30 k
768
in
AGL060
60 k
1,536
AGL125
125 k
3,072
AGL250
250 k
6,144
AGL600
600 k
13,824
AGL1000
1M
24,576
IGLOO Devices
System Gates
VersaTiles (D-Flip-Flops)
Quiescent Current (typical)
Flash*Freeze Mode (µA)
RAM kbits (1,024 bits)
4,608 Bit Blocks
FlashROM Bits
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals
1
I/O Banks
Maximum User I/Os
Package Pins
CS
QFN
VQFP
FBGA
4
–
–
1k
–
–
6
2
81
8
18
4
1k
Yes
1
18
2
96
CS196
QN132
VQ100
FG144
14
36
8
1k
Yes
1
18
2
133
CS196
QN132
VQ100
FG144
28
36
8
1k
Yes
1
18
4
143
CS196
QN132
VQ100
FG144
60
108
24
1k
Yes
1
18
4
235
102
144
32
1k
Yes
1
18
4
300
QN132
VQ100
FG144, FG256,
FG484
FG144, FG256,
FG484
Notes:
1. Six chip (main) and three quadrant global networks are available for AGL060 and above.
2. For higher densities and support of additional features, refer to the
IGLOOe Flash FPGAs
datasheet.
May 2007
© 2007 Actel Corporation
1
See the Actel website for the latest version of the datasheet.
IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
Introduction and Overview
General Description
The IGLOO family of Flash FPGAs, based on a 130-nm
Flash process, offers the lowest power FPGA, a single-
chip
solution,
small
footprint
packages,
reprogrammability, and an abundance of advanced
features.
The Low Power Active capability (static idle) allows for
ultra-low power consumption (from 25 µW) while the
IGLOO device is completely functional in the system by
maintaining I/O, SRAM, registers, and logic functions.
This allows the IGLOO device to control the system
power management based on external inputs (e.g.,
scanning for keyboard stimulus) while consuming
minimal power.
The Flash*Freeze technology used in IGLOO devices
allows entering and exiting an ultra-low power mode
that consumes as little as 5 µW while retaining SRAM
and register data. Flash*Freeze technology simplifies
power management through I/O and clock management
with rapid recovery to operation mode.
Nonvolatile Flash technology gives IGLOO devices the
advantage of being a secure, low power, single-chip
solution that is live at power-up (LAPU). IGLOO is
reprogrammable and offers time to market benefits at
an ASIC-level unit cost.
These features enable designers to create high-density
systems using existing ASIC or FPGA design flows and
tools.
IGLOO devices offer 1 kbit of on-chip, reprogrammable,
nonvolatile FlashROM memory storage as well as clock
conditioning circuitry based on an integrated phase-
locked loop (PLL). The AGL030 device has no PLL or RAM
support. IGLOO devices have up to 1 million system
gates, supported with up to 144 kbits of true dual-port
SRAM, and up to 288 user I/Os.
power consumption, thus achieving the lowest total
system power.
Flash*Freeze technology allows the user to keep all power
supplies, I/Os, and clocks connected to the device in normal
operation. When the IGLOO device enters Flash*Freeze
mode, the device automatically shuts off the clocks and
inputs to the FPGA core; when the device exits Flash*Freeze
mode, all activity resumes and data is retained.
This
low
power
feature,
combined
with
reprogrammability, a single-chip and single-voltage
solution, and availability of small-footprint, high
pin-count packages, makes IGLOO devices the best fit for
portable electronics.
Flash Advantages
Low Power
Flash-based IGLOO devices exhibit power characteristics
similar to those of an ASIC, making them an ideal choice
for power-sensitive applications. IGLOO devices have
only a very limited power-on current surge and no high-
current transition period, both of which occur on many
FPGAs.
IGLOO devices also have low dynamic power
consumption to further maximize power savings, which
is also reduced by the use of 1.2 V core voltage.
Low dynamic power consumption, combined with low
static power consumption and Flash*Freeze technology,
makes the IGLOO device the lowest total system power
offered by any FPGA.
Security
The nonvolatile, Flash-based IGLOO devices do not
require a boot PROM, so there is no vulnerable external
bitstream that can be easily copied. IGLOO devices
incorporate FlashLock, which provides a unique
combination of reprogrammability and design security
without external overhead, advantages that only an
FPGA with nonvolatile Flash programming can offer.
IGLOO devices utilize a 128-bit Flash-based lock and a
separate AES key to secure programmed intellectual
property and configuration data. In addition, all
FlashROM data in the IGLOO devices can be encrypted
prior to loading, using the industry-leading AES-128
(FIPS192) bit block cipher encryption standard. The AES
standard was adopted by the National Institute of
Standards and Technology (NIST) in 2000, and replaces
the 1977 DES standard. IGLOO devices have a built-in AES
Flash*Freeze Technology
The IGLOO device offers unique Flash*Freeze technology
that allows the IGLOO device to enter and exit an ultra-
low power mode. IGLOO devices do not need additional
components to turn off I/Os or clocks while retaining the
design information, SRAM content, and registers. The
Flash*Freeze technology is combined with in-system
programmability, which allows users to quickly and easily
upgrade and update the design in the final stages of
manufacturing or in the field. The ability of IGLOO to
support 1.2 V core voltage allows further reduction of
P ro du c t B ri ef
5
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