PIC18F2XJXX/4XJXX FAMILY
Flash Microcontroller Programming Specification
1.0
DEVICE OVERVIEW
2.0
PROGRAMMING OVERVIEW
OF THE PIC18F2XJXX/4XJXX
FAMILY
This document includes the programming specifications
for the following devices:
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PIC18F24J10
PIC18F25J10
PIC18F44J10
PIC18F45J10
PIC18F24J11
PIC18F25J11
PIC18F26J11
PIC18F44J11
PIC18F45J11
PIC18F46J11
PIC18F26J13
PIC18F27J13
PIC18F46J13
PIC18F47J13
PIC18F24J50
PIC18F25J50
PIC18F26J50
PIC18F44J50
PIC18F45J50
PIC18F46J50
PIC18F26J53
PIC18F27J53
PIC18F46J53
PIC18F47J53
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PIC18LF24J10
PIC18LF25J10
PIC18LF44J10
PIC18LF45J10
PIC18LF24J11
PIC18LF25J11
PIC18LF26J11
PIC18LF44J11
PIC18LF45J11
PIC18LF46J11
PIC18LF26J13
PIC18LF27J13
PIC18LF46J13
PIC18LF47J13
PIC18LF24J50
PIC18LF25J50
PIC18LF26J50
PIC18LF44J50
PIC18LF45J50
PIC18LF46J50
PIC18LF26J53
PIC18LF27J53
PIC18LF46J53
PIC18LF47J53
The PIC18F2XJXX/4XJXX family devices are
programmed using In-Circuit Serial Programming™
(ICSP™). This programming specification applies to
devices of the PIC18F2XJXX/4XJXX family in all
package types.
2.1
Pin Diagrams
The pin diagrams for the PIC18F2XJXX/4XJXX family
are shown in Figure 2-1 and Figure 2-2. The pins that
are required for programming are listed in Table 2-1
and shown in darker lettering in the diagrams.
TABLE 2-1:
Pin Name
MCLR
V
DD
and AV
DD
(1)
SS
and AV
SS
(1)
V
V
DDCORE
/V
CAP
RB6
RB7
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F2XJXX/4XJXX FAMILY
During Programming
Pin Name
MCLR
V
DD
V
SS
V
DDCORE
V
CAP
PGC
PGD
Pin Type
P
P
P
P
I
I
I/O
Programming Enable
Power Supply
Ground
Regulated Power Supply for Microcontroller Core
Filter Capacitor for On-Chip Voltage Regulator
Serial Clock
Serial Data
Pin Description
Legend:
I = Input, O = Output, P = Power
Note 1:
All power supply and ground pins must be connected, including analog supplies (AV
DD
) and ground
(AV
SS
).
©
2009 Microchip Technology Inc.
DS39687E-page 1
PIC18F2XJXX/4XJXX FAMILY
FIGURE 2-1:
PIC18F2XJXX/4XJXX FAMILY PIN DIAGRAMS
28-Pin SPDIP, SOIC, SSOP
MCLR
RA0
RA1
RA2
RA3
V
DDCORE
/V
CAP
RA5
V
SS
OSC1
OSC2
RC0
RC1
RC2
RC3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/PGD
RB6/PGC
RB5
RB4
RB3
RB2
RB1
RB0
V
DD
V
SS
RC7
RC6
RC5
RC4
28-Pin QFN
RA1
RA0
MCLR
RB7/PGD
RB6/PGC
RB5
RB4
28 27 26 25 24 23 22
RA2
RA3
V
DDCORE
/V
CAP
RA5
V
SS
OSC1/CLKI
OSC2/CLKO
1
2
3
4
5
6
7
21
20
19
18
17
16
15
RB3
RB2
RB1
RB0
V
DD
V
SS
RC7
PIC18F2XJ1X
PIC18F2XJ5X
8 9 10 11 12 13 14
RC0
RC1
RC2
RC3
RC4
RC5
RC6
PIC18F2XJ1X
PIC18F2XJ5X
DS39687E-page 2
©
2009 Microchip Technology Inc.
PIC18F2XJXX/4XJXX FAMILY
FIGURE 2-2:
PIC18F2XJXX/4XJXX FAMILY PIN DIAGRAMS (CONTINUED)
40-Pin PDIP
MCLR
RA0
RA1
RA2
RA3
V
DDCORE
/V
CAP
RA5
RE0
RE1
RE2
V
DD
V
SS
OSC1
OSC2
RC0
RC1
RC2
RC3
RD0
RD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/PGD
RB6/PGC
RB5
RB4
RB3
RB2
RB1
RB0
V
DD
V
SS
RD7
RD6
RD5
RD4
RC7
RC6
RC5
RC4
RD3
RD2
PIC18F4XJ1X
44-Pin QFN
44
43
42
41
40
39
38
37
36
35
34
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
44
43
42
41
40
39
38
37
36
35
34
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC
44-Pin TQFP
©
2009 Microchip Technology Inc.
NC
NC
RB4
RB5
RB6/PGC
RB7/PGD
MCLR
RA0
RA1
RA2
RA3
12
13
14
15
16
17
18
19
20
21
22
RC7
RD4
RD5
RD6
RD7
V
SS
V
DD
RB0
RB1
RB2
RB3
1
2
3
4
5
6
7
8
9
10
11
PIC18F4XJ1X
PIC18F4XJ5X
33
32
31
30
29
28
27
26
25
24
23
NC
RC0
OSC2
OSC1
V
SS
V
DD
RE2
RE1
RE0
RA5
V
DDCORE
/V
CAP
RB3
NC
RB4
RB5
RB6/PGC
RB7/PGD
MCLR
RA0
RA1
RA2
RA3
12
13
14
15
16
17
18
19
20
21
22
RC7
RD4
RD5
RD6
RD7
V
SS
AV
DD
V
DD
RB0
RB1
RB2
1
2
3
4
5
6
7
8
9
10
11
PIC18F4XJ1X
PIC18F4XJ5X
33
32
31
30
29
28
27
26
25
24
23
OSC2
OSC1
V
SS
AV
SS
V
DD
AV
DD
RE2
RE1
RE0
RA5
V
DDCORE
/V
CAP
DS39687E-page 3
PIC18F2XJXX/4XJXX FAMILY
2.1.1
PIC18F2XJXX/4XJXX/
LF2XJXX/LF4XJXX DEVICES AND
THE ON-CHIP VOLTAGE
REGULATOR
2.2
Memory Maps
PIC18FXXJXX devices have an internal core voltage
regulator. On these devices (“PIC18F” in the part num-
ber), the regulator is always enabled. The regulator
input is taken from the microcontroller V
DD
pins. The
output of the regulator is supplied to the V
DDCORE
/V
CAP
pin. On these devices, this pin simultaneously serves
as both the regulator output and the microcontroller
core power input pin. For these devices, the
V
DDCORE
/V
CAP
pin should be tied to a capacitor and
nothing else.
PIC18LFXXJXX devices do not have an internal core
voltage regulator. On these devices (“PIC18LF” in the
part number), power must be externally supplied to
both V
DD
and V
DDCORE
/V
CAP
.
Whether or not the regulator is used, it is always good
design practice to have sufficient capacitance on all
supply pins. Examples are shown in Figure 2-3.
The specifications for core voltage and capacitance are
listed in
Section 6.0 “AC/DC Characteristics Timing
Requirements for Program/Verify Test Mode”.
The PIC18F2XJXX/4XJXX family of devices offers
program memory sizes of 16, 32, 64 and 128 Kbytes.
The memory sizes for different members of the family
are shown in Table 2-2. The overall memory maps for
all the devices are shown in Figure 2-4.
TABLE 2-2:
PROGRAM MEMORY SIZES
FOR PIC18F2XJXX/4XJXX
FAMILY DEVICES
Program
Memory
(Kbytes)
Location of Flash
Configuration
Words
Device*
PIC18F24J10
PIC18F44J10
PIC18F24J11
PIC18F44J11
PIC18F24J50
PIC18F44J50
PIC18F25J10
PIC18F45J10
PIC18F25J11
PIC18F45J11
PIC18F25J50
PIC18F45J50
PIC18F26J11
PIC18F46J11
PIC18F26J13
PIC18F46J13
PIC18F26J50
PIC18F46J50
PIC18F26J53
PIC18F46J53
PIC18F27J13
PIC18F47J13
PIC18F27J53
PIC18F47J53
*
16
3FF8h:3FFFh
32
7FF8h:7FFFh
FIGURE 2-3:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
PIC18F2XJXX/4XJXX Devices (Regulator Enabled)
3.3V
PIC18F2XJXX/4XJXX
V
DD
V
DDCORE
/V
CAP
C
F
V
SS
64
FFF8h:FFFFh
PIC18LF2XJXX/4XJXX Devices (Regulator Disabled)
(V
DD
=
V
DDCORE
)
2.5V
PIC18LF2XJXX/4XJXX
V
DD
V
DDCORE
/V
CAP
V
SS
128
1FFF8h:1FFFFh
Includes PIC18F and PIC18LF devices.
(V
DD
≥
V
DDCORE
)
2.5V 3.3V
PIC18LF2XJXX/4XJXX
V
DD
V
DDCORE
/V
CAP
V
SS
For purposes of code protection, the program memory
for every device is treated as a single block. Enabling
code protection, thus protects the entire code memory,
and not individual segments.
DS39687E-page 4
©
2009 Microchip Technology Inc.
PIC18F2XJXX/4XJXX FAMILY
The Configuration Words for these devices are located
at addresses, 300000h through 300007h. These are
implemented as three pairs of volatile memory regis-
ters. Each register is automatically loaded from a copy
stored at the end of program memory. For this reason,
the last four words (or eight bytes) of the code space
(also called the Flash Configuration Words) should be
written with configuration data and not executable
code. The addresses of the Flash Configuration Words
are also listed in Table 2-2. Refer to section
Section 5.0
“Configuration Word”
for more information.
Locations, 3FFFFEh and 3FFFFFh, are reserved for
the device ID bits. These bits may be used by the
programmer to identify what device type is being pro-
grammed and are described in
Section 5.1 “Device ID
Word”.
These device ID bits read out normally, even
after code protection.
2.2.1
MEMORY ADDRESS POINTER
Memory in the device address space (000000h to
3FFFFFh) is addressed via the Table Pointer register,
which in turn, is comprised of three registers:
• TBLPTRU at RAM address 0FF8h
• TBLPTRH at RAM address 0FF7h
• TBLPTRL at RAM address 0FF6h
TBLPTRU
Addr[21:16]
TBLPTRH
Addr[15:8]
TBLPTRL
Addr[7:0]
The 4-bit command, ‘0000’ (core instruction), is used to
load the Table Pointer prior to using many read or write
operations.
©
2009 Microchip Technology Inc.
DS39687E-page 5
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