Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
FEATURES
•
Fast locking by ‘Fractional-N’ divider
•
Auxiliary synthesizer
•
Digital phase comparator with proportional and integral
charge pump output
•
High-speed serial input
•
Low-power consumption
•
Programmable charge pump currents
•
Supply voltage range 2.9 to 5.5 V.
APPLICATIONS
•
Mobile telephony
•
Portable battery-powered radio equipment.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
UMA1005T
SSOP20
DESCRIPTION
GENERAL DESCRIPTION
UMA1005T
The UMA1005T is a low-power, high-performance dual
frequency synthesizer fabricated in CMOS technology.
Fractional-N division with selectable modulo 5 or 8 is
implemented in the main synthesizer.
The detectors and charge pumps are designated to
achieve 10 to 5000 kHz channel spacing using
fractional-N decreases the channel spacing by a factor
5 or 8. Together with an external standard 2, 3 or 4 ratio
prescaler the main synthesizer can operate in the GHz
frequency range.
Channel selection and programming is realized by a
high-speed 3-wire serial interface.
VERSION
SOT266-1
plastic shrink small outline package; 20 leads; body width 4.4 mm
November 1994
2
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
PINNING
SYMBOL PIN
V
DDD
INM1
INM2
DATA
CLOCK
STROBE
INR
INA
RA
PHA
PHI
V
SSA
PHP
V
DDA
RN
RF
LOCK
FB1
FB2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DESCRIPTION
digital supply voltage
main divider positive input; rising edge
active
main divider negative input; falling
edge active
serial data input line
serial clock input line
serial strobe input line
reference divider input line; rising edge
active
auxiliary divider input line; rising edge
active
auxiliary current setting; resistor to V
SS
auxiliary phase detector output
integral phase detector output
analog ground; internally connected to
V
SS
proportional phase detector output
analog supply voltage
main current setting input; resistor to
V
SS
fractional compensation current setting
input; resistor to V
SS
lock detector output
feedback output 1 for prescaler
modulus control
feedback output 2 for prescaler
modulus control
common ground connection
INM2
DATA
CLOCK
STROBE
INR
INA
RA
3
4
5
UMA1005T
6
7
8
9
15
14
13
12
11
MEA667
UMA1005T
1/2 page (Datasheet)
V DDD
INM1
1
2
20 V SS
19
18
17
16
FB2
FB1
LOCK
RF
RN
V DDA
PHP
V SSA
PHI
22 mm
PHA 10
Fig.2 Pin configuration.
November 1994
4
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
FUNCTIONAL DESCRIPTION
Serial programming input
The serial input is a 3-wire input (CLOCK, STROBE and
DATA) to program all counter ratios, DACs, selection and
enable bits. The programming data is structured into
24 or 32-bit words. Each word includes 1 or 4 address
bits. Figure 3 shows the timing diagram of the serial input.
When the STROBE = LOW, the clock driver is enabled
and on the positive edges of the CLOCK the signal on the
DATA input is clocked into a shift register. When the
STROBE = HIGH, the clock is disabled and the data in the
shift register remains stable. Depending on the
1 or 4 address bits the data is latched into different
working registers or temporary registers. In order to fully
program the synthesizer, 4 words must be sent:
1. D word.
2. C word.
3. B word.
4. A word.
Figure 4 shows the format and the contents of each word.
The E word is for testing purposes only. The E (test) word
UMA1005T
is reset when programming the D word. The data for NM4,
CN and PR is stored by the B word temporary registers.
When the A word is loaded, the data of these temporary
registers is loaded together with the A word into the work
registers which avoids false temporary main divider input.
CN is only loaded from the temporary registers when a
short 24-bit A0 word is used. CN will be directly loaded by
programming a long 32-bit A1 word. The flag LONG in the
D word determines whether A0 (LONG = 0) or A1
(LONG = 1) format is applicable.
The A word contains new data for the main divider. The
A word is loaded only when a main divider synchronization
signal is also active, to avoid phase jumps when
reprogramming the main divider. The synchronization
signal is generated by the main divider. It disables the
loading of the A word each main divider cycle during
maximum 300 main divider input cycles. To make sure
that the A word will be correctly loaded the STROBE signal
must be HIGH for at least 300 main divider input cycles.
Programming the A word also means that the main charge
pumps on outputs PHP and PHI are set into the speed-up
mode as long as the STROBE remains HIGH.
handbook, full pagewidth
data
valid
data
change
VH
DATA
D0
t suDA
t hDA
D1
D30
t HC
D31
VL
t LC
VH
CLOCK
VL
t suST
STROBE
VL
clock enabled
shift in data
clock disabled
store data
MBE121
t hST
VH
Fig.3 Serial input timing sequence.
November 1994
5
Analog electronics
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